INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL SHARED GATE HIGH-DRIVE THIN FILM TRANSISTORS
Structures having vertical shared gate high-drive thin film transistors are described. In an example, an integrated circuit structure includes a stack of alternating dielectric layers and metal layers. A trench is through the stack of alternating dielectric layers and metal layers. A semiconductor channel layer is along sides of the trench. A gate dielectric layer is along sides the semiconductor channel layer in the trench. A gate electrode is within sides of the gate dielectric layer.
1 . An integrated circuit structure, comprising:
a stack of alternating dielectric layers and metal layers;
a trench through the stack of alternating dielectric layers and metal layers;
a semiconductor channel layer along sides and a bottom of the trench;
a gate dielectric layer along sides and on a bottom of the semiconductor channel layer in the trench; and
a gate electrode within sides and on a bottom of the gate dielectric layer.
2 . The integrated circuit structure of claim 1 , wherein an uppermost layer of the stack of alternating dielectric layers and metal layers is a dielectric layer, and the semiconductor channel layer extends along a top of the top dielectric layer.
3 . The integrated circuit structure of claim 1 , wherein the gate electrode is accessible for electrical contact from a top side of the stack of alternating dielectric layers and metal layers.
4 . The integrated circuit structure of claim 1 , wherein the metal layers include successive drain layers above successive source layers.
5 . The integrated circuit structure of claim 1 , wherein the semiconductor channel layer is selected from the group consisting of poly-silicon, non-crystalline silicon, germanium, a group III-V material, MoS 2 , WSe 2 , MoS 2 , WSe 2 , InS, HfS, ZnS, ZnSe, In 2 O 3 , ZnO, AZO, IGZO, and IZO.
6 . An integrated circuit structure, comprising:
a stack of alternating dielectric layers and metal layers;
a trench through the stack of alternating dielectric layers and metal layers;
a semiconductor channel layer along sides and not along a bottom of the trench;
a gate dielectric layer along sides of the semiconductor channel layer and not along a bottom of the trench; and
a gate electrode within sides of the gate dielectric layer.
7 . The integrated circuit structure of claim 6 , wherein an uppermost layer of the stack of alternating dielectric layers and metal layers is a dielectric layer, and the semiconductor channel layer extends into the top dielectric layer.
8 . The integrated circuit structure of claim 6 , wherein the gate electrode is accessible for electrical contact from a bottom side of the stack of alternating dielectric layers and metal layers.
9 . The integrated circuit structure of claim 6 , wherein the metal layers include successive drain layers above successive source layers.
10 . The integrated circuit structure of claim 6 , wherein the semiconductor channel layer is selected from the group consisting of poly-silicon, non-crystalline silicon, germanium, a group III-V material, MoS 2 , WSe 2 , MoS 2 , WSe 2 , InS, HfS, ZnS, ZnSe, In 2 O 3 , ZnO, AZO, IGZO, and IZO.
11 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a stack of alternating dielectric layers and metal layers;
a trench through the stack of alternating dielectric layers and metal layers;
a semiconductor channel layer along sides and a bottom of the trench;
a gate dielectric layer along sides and on a bottom of the semiconductor channel layer in the trench; and
a gate electrode within sides and on a bottom of the gate dielectric layer.
12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.
13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a stack of alternating dielectric layers and metal layers;
a trench through the stack of alternating dielectric layers and metal layers;
a semiconductor channel layer along sides and not along a bottom of the trench;
a gate dielectric layer along sides of the semiconductor channel layer and not along a bottom of the trench; and
a gate electrode within sides of the gate dielectric layer.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.