Three-dimensional memory with stacked select-gate structures
A three-dimensional memory includes a bottom select gate structure, a stack structure disposed on the bottom select gate structure, and a top select gate structure disposed on the stack structure. The stack structure includes a channel layer extending in stack structure in the first direction of the thickness of the stack structure. The channel layer has a first conductive type impurity. At least one of the bottom select gate structure or the top select gate structure includes a semiconductor structure extending in the first direction and connected with the channel layer and having a second conductive type impurity different from the first conductive type impurity.
1 . A three-dimensional memory, comprising:
a bottom select gate structure;
a stack structure disposed on the bottom select gate structure and comprising a channel layer extending in the stack structure in a first direction, the channel layer having a first conductive type impurity, the first direction being a direction of a thickness of the stack structure; and
a top select gate structure disposed on the stack structure,
wherein
at least one of the bottom select gate structure or the top select gate structure comprises a semiconductor structure extending in the first direction and connected with the channel layer, the semiconductor structure having a second conductive type impurity different from the first conductive type impurity;
the bottom select gate structure comprises at least one first stack layer each comprising a bottom select gate layer and a bottom dielectric layer;
the top select gate structure comprises at least one second stack layer each comprising a top select gate layer and a top dielectric layer;
at least one of the bottom select gate layer or the top select gate layer is a semiconductor gate layer; and
an impurity doping concentration of the semiconductor gate layer is greater than an impurity doping concentration of the semiconductor structure.
2 . The three-dimensional memory of claim 1 , wherein
the semiconductor structure is a first semiconductor fill layer disposed in the bottom select gate structure; and
the bottom select gate structure comprises:
the first semiconductor fill layer extending in the first direction; and
a first barrier layer disposed on a sidewall of the first semiconductor fill layer.
3 . The three-dimensional memory of claim 1 , wherein
the semiconductor structure is a first semiconductor thin film layer disposed in the bottom select gate structure; and
the bottom select gate structure comprises:
a first insulating dielectric fill layer extending in the first direction; and
the first semiconductor thin film layer and a first barrier layer, in sequence, disposed on a sidewall of the first insulating dielectric fill layer.
4 . The three-dimensional memory of claim 1 , wherein
the semiconductor structure is a first semiconductor fill layer or a first semiconductor thin film layer;
the three-dimensional memory further comprises a semiconductor connect layer located below and connected with the first semiconductor fill layer or the first semiconductor thin film layer; and
the semiconductor connect layer has the first conductive type impurity.
5 . The three-dimensional memory of claim 4 , wherein an impurity doping concentration of the semiconductor connect layer is greater than an impurity doping concentration of the first semiconductor fill layer or the first semiconductor thin film layer.
6 . The three-dimensional memory of claim 1 , wherein
the semiconductor structure is a second semiconductor fill layer disposed in the top select gate structure; and
the top select gate structure comprises:
the second semiconductor fill layer extending in the first direction, and a conductive plug located above the second semiconductor fill layer and connected with the second semiconductor fill layer; and
a second barrier layer disposed on a sidewall of the second semiconductor fill layer.
7 . The three-dimensional memory of claim 1 , wherein
the semiconductor structure is a second semiconductor thin film layer disposed in the top select gate structure;
the top select gate structure comprises:
a second insulating dielectric fill layer extending in the first direction; and
the second semiconductor thin film layer and a second barrier layer, in sequence, disposed on a sidewall of the second insulating dielectric fill layer, a conductive plug being located above the second semiconductor thin film layer and the second insulating dielectric fill layer and connected with the second semiconductor thin film layer.
8 . The three-dimensional memory of claim 7 , wherein
the semiconductor structure is a second semiconductor fill layer or the second semiconductor thin film layer, disposed in the top select gate structure;
the three-dimensional memory further comprises a channel plug located above the channel layer, the channel layer being connected with the second semiconductor fill layer or the second semiconductor thin film layer through the channel plug; and
both the conductive plug and the channel plug have the first conductive type impurity.
9 . The three-dimensional memory of claim 8 , wherein impurity doping concentrations of both the conductive plug and the channel plug are greater than an impurity doping concentration of the second semiconductor fill layer or the second semiconductor thin film layer.
10 . The three-dimensional memory of claim 1 , wherein
one of the bottom select gate layer and the top select gate layer is a semiconductor gate layer; and
another one of the bottom select gate layer or the top select gate layer is a metal gate layer.
11 . The three-dimensional memory of claim 1 , wherein
the semiconductor structure is a first semiconductor fill layer or a first semiconductor thin film layer located in the bottom select gate structure;
the three-dimensional memory further comprises a semiconductor connect layer located below and connected with the first semiconductor fill layer or the first semiconductor thin film layer;
the first semiconductor fill layer or the first semiconductor thin film layer has an impurity doping concentration of 10 13 cm −3 to 10 15 cm −3 ;
the semiconductor connect layer has an impurity doping concentration of 10 19 cm −3 to 10 21 cm −3 ; and
the semiconductor gate layer has an impurity doping concentration of 10 19 cm −3 to 10 21 cm −3 .
12 . The three-dimensional memory of claim 1 , wherein
the semiconductor structure is a second semiconductor fill layer or a second semiconductor thin film layer located in the top select gate structure;
the three-dimensional memory further comprises:
a conductive plug located above and connected with the second semiconductor fill layer or the second semiconductor thin film layer; and
a channel plug located above the channel layer, the channel layer being connected with the second semiconductor fill layer or the second semiconductor thin film layer through the channel plug;
the second semiconductor fill layer or the second semiconductor thin film layer has an impurity doping concentration of 10 13 cm −3 to 10 15 cm −3 ;
the conductive plug and the channel plug have impurity doping concentrations of 10 19 cm −3 to 10 21 cm −3 ; and
the semiconductor gate layer has an impurity doping concentration of 10 19 cm −3 to 10 21 cm −3 .
13 . The three-dimensional memory of claim 1 , wherein
the bottom select gate structure comprises at least two of the at least one first stack layer; or
the top select gate structure comprises at least two of the at least one second stack layer.
14 . The three-dimensional memory of claim 1 , wherein
the semiconductor structure is one of a second semiconductor fill layer or a second semiconductor thin film layer, located in the top select gate structure; and
the three-dimensional memory further comprises a channel plug located above the channel layer and connected with the one of the second semiconductor fill layer or the second semiconductor thin film layer through the channel plug, the channel plug being arranged between the channel layer and the one of the second semiconductor fill layer or the second semiconductor thin film layer.
15 . The three-dimensional memory of claim 1 , wherein
the semiconductor structure is one of a second semiconductor fill layer or a second semiconductor thin film layer, located in the top select gate structure; and
a conductive plug is disposed above the one of the second semiconductor fill layer or the second semiconductor thin film layer, a second barrier layer surrounding sidewalls of the conductive plug and the one of the second semiconductor fill layer or the second semiconductor thin film layer.
16 . The three-dimensional memory of claim 1 , wherein
the semiconductor structure is one of a first semiconductor fill layer or a first semiconductor thin film layer, located in the bottom select gate structure; and
the three-dimensional memory further comprises a semiconductor connect layer, the one of the first semiconductor fill layer or the first semiconductor thin film layer extending in the first direction into the semiconductor connect layer.
17 . The three-dimensional memory of claim 16 , wherein
a first barrier layer is configured to surround a sidewall of the one of the first semiconductor fill layer or the first semiconductor thin film layer, without extending into the semiconductor connect layer.
18 . The three-dimensional memory of claim 1 , wherein
the bottom select gate structure is aligned with the top select gate structure.
19 . The three-dimensional memory of claim 1 , wherein
each of the bottom select gate layer and the top select gate layer is a semiconductor gate layer.
20 . A memory system, comprising:
a three-dimensional memory comprising:
a bottom select gate structure;
a stack structure disposed on the bottom select gate structure and comprising a channel layer extending in the stack structure in a first direction, the channel layer having a first conductive type impurity, the first direction being a direction of a thickness of the stack structure; and
a top select gate structure disposed on the stack structure,
wherein
at least one of the bottom select gate structure or the top select gate structure comprises a semiconductor structure extending in the first direction and connected with the channel layer, the semiconductor structure having a second conductive type impurity different from the first conductive type impurity;
the bottom select gate structure comprises at least one first stack layer each comprising a bottom select gate layer and a bottom dielectric layer;
the top select gate structure comprises at least one second stack layer each comprising a top select gate layer and a top dielectric layer;
at least one of the bottom select gate layer or the top select gate layer is a semiconductor gate layer; and
an impurity doping concentration of the semiconductor gate layer is greater than an impurity doping concentration of the semiconductor structure; and
a controller coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data.