Cell-based signal connectivity between wafer frontside and backside
A semiconductor structure includes a first backside metal rail that extends across the structure and a second backside metal rail parallel and adjacent to the first backside metal rail. The first and second backside metal rails bound a first circuit row. The structure also includes a backside signal wire that interrupts the second backside metal rail; and a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail. The second and third backside metal rails bound a second circuit row. The structure also includes gate metal pitches, which extend across the structure perpendicular to the backside metal rails. The structure also includes a frontside signal wire above the gate metal pitches; and a signal via that penetrates the structure and connects the backside signal wire to the frontside signal wire.
1 . A semiconductor structure comprising:
a first backside metal rail that extends across the structure in a first direction;
a second backside metal rail that extends across the structure parallel and adjacent to the first backside metal rail, wherein the first and second backside metal rails bound a first circuit row;
a backside signal wire that interrupts the second backside metal rail;
a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail, wherein the second and third backside metal rails bound a second circuit row;
adjacent and parallel gate metal pitches that extend across the structure perpendicular to and above the first, second, and third backside metal rails, wherein the gate metal pitches define a width of a signal transfer cell that occupies the first and second circuit rows;
a frontside signal wire that extends across the structure above the gate metal pitches; and
a signal via that penetrates the structure perpendicular to the first, second, and third backside metal rails and to the gate metal pitches and that connects the backside signal wire to the frontside signal wire.
2 . The semiconductor structure of claim 1 , wherein the signal via is disposed in a space between two adjacent ones of the gate metal pitches.
3 . The semiconductor structure of claim 1 , further comprising:
peripheral vias that penetrate the structure perpendicular to the first, second, and third backside metal rails and to the gate metal pitches and in registry with the first, second, and third backside metal rails at edges of the signal transfer cell, wherein locations of the peripheral vias and the signal via define an X.
4 . The semiconductor structure of claim 1 , further comprising:
local interconnects that are disposed vertically between the gate metal pitches and the frontside signal wire and that are electrically connected between the signal via and the frontside signal wire.
5 . The semiconductor structure of claim 4 , further comprising:
a signal contact that is electrically connected between the local interconnects and the signal via.
6 . The semiconductor structure of claim 5 , wherein the signal contact extends perpendicular to the first, second, and third backside metal rails.
7 . The semiconductor structure of claim 6 , wherein the signal contact is contained within the signal transfer cell.
8 . The semiconductor structure of claim 1 , further comprising a negative-doped well in the structure, wherein the signal via penetrates the negative-doped well.
9 . The semiconductor structure of claim 1 , wherein lengths of the first, second, and third backside metal rails are in a same plane.
10 . The semiconductor structure of claim 1 , further comprising:
a complementary metal-oxide-semiconductor inverter cell that is connected between the second and third backside metal rails, adjacent to the signal transfer cell.
11 . The semiconductor structure of claim 1 , wherein the second backside metal rail is interrupted by cuts at either side of the signal via.
12 . The semiconductor structure of claim 11 , wherein each of the cuts is disposed beyond an edge of the signal transfer cell.
13 . The semiconductor structure of claim 1 , wherein the signal transfer cell is free of logic circuitry.
14 . The semiconductor structure of claim 1 , wherein the signal via is centered in the signal transfer cell.
15 . The semiconductor structure of claim 1 , wherein the frontside signal wire is broken into left, middle, and right segments, wherein the middle segment connects to the signal via in the signal transfer cell while the left and right segments extend outside the signal transfer cell.
16 . The semiconductor structure of claim 15 , wherein portions of the left and right segments of the frontside signal wire extend within the signal transfer cell.
17 . A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of an integrated circuit, wherein the HDL design structure comprises:
a first backside metal rail that extends across the structure in a first direction;
a second backside metal rail that extends across the structure parallel and adjacent to the first backside metal rail, wherein the first and second backside metal rails bound a first circuit row;
a backside signal wire that interrupts the second backside metal rail;
a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail, wherein the second and third backside metal rails bound a second circuit row;
adjacent and parallel gate metal pitches that extend across the structure perpendicular to and above the first, second, and third backside metal rails, wherein the gate metal pitches define a width of a signal transfer cell that occupies the first and second circuit rows;
a frontside signal wire that extends across the structure above the gate metal pitches; and
a signal via that penetrates the structure perpendicular to the first, second, and third backside metal rails and to the gate metal pitches and that connects the backside signal wire to the frontside signal wire.
18 . The HDL design structure of claim 17 , wherein the signal via is disposed in a space between two adjacent ones of the gate metal pitches.
19 . The HDL design structure of claim 17 , further comprising:
peripheral vias that penetrate the structure perpendicular to the first, second, and third backside metal rails and to the gate metal pitches and in registry with the first, second, and third backside metal rails at edges of the signal transfer cell, wherein locations of the peripheral vias and the signal via define an X.
20 . The HDL design structure of claim 17 , further comprising:
local interconnects that are disposed vertically between the gate metal pitches and the frontside signal wire and that are electrically connected between the signal via and the frontside signal wire.
21 . The HDL design structure of claim 20 , further comprising:
a signal contact that is electrically connected between the local interconnects and the signal via.