GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOLATION
Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.
1 . An integrated circuit structure, comprising:
a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls;
an isolation structure on the top and along the sidewalls of the sub-fin structure;
a vertical arrangement of horizontal nanowires on the isolation structure and vertically over the top surface of the sub-fin structure; and
a gate endcap structure parallel with the vertical arrangement of horizontal nanowires, wherein a portion of the gate endcap structure is continuous with a portion of the isolation structure vertically between the sub-fin structure and the vertical arrangement of horizontal nanowires.
2 . The integrated circuit structure of claim 1 , wherein the gate endcap structure comprises an upper portion on the portion of the gate endcap structure continuous with the portion of the isolation structure vertically between the sub-fin structure and the vertical arrangement of horizontal nanowires.
3 . The integrated circuit structure of claim 1 , wherein a portion of the isolation structure along a first of the sidewalls of the sub-fin structure is discontinuous with a portion of the isolation structure along a second of the sidewalls of the sub-fin structure.
4 . The integrated circuit structure of claim 1 , further comprising:
a gate stack surrounding a channel region of the vertical arrangement of horizontal nanowires.
5 . The integrated circuit structure of claim 4 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
6 . The integrated circuit structure of claim 1 , further comprising:
a pair of non-discrete epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal nanowires.
7 . The integrated circuit structure of claim 1 , further comprising:
a pair of discrete epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal nanowires.
8 . A method of fabricating an integrated circuit structure, the method comprising:
forming a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls;
forming an isolation structure on the top and along the sidewalls of the sub-fin structure;
forming a vertical arrangement of horizontal nanowires on the isolation structure and vertically over the top surface of the sub-fin structure; and
forming a gate endcap structure parallel with the vertical arrangement of horizontal nanowires, wherein a portion of the gate endcap structure is continuous with a portion of the isolation structure vertically between the sub-fin structure and the vertical arrangement of horizontal nanowires.
9 . The method of claim 8 , wherein the gate endcap structure comprises an upper portion on the portion of the gate endcap structure continuous with the portion of the isolation structure vertically between the sub-fin structure and the vertical arrangement of horizontal nanowires.
10 . The method of claim 8 , wherein a portion of the isolation structure along a first of the sidewalls of the sub-fin structure is discontinuous with a portion of the isolation structure along a second of the sidewalls of the sub-fin structure.
11 . The method of claim 8 , further comprising:
forming a gate stack surrounding a channel region of the vertical arrangement of horizontal nanowires.
12 . The method of claim 11 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
13 . The method of claim 8 , further comprising:
forming a pair of non-discrete epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal nanowires.
14 . The method of claim 8 , further comprising:
forming a pair of discrete epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal nanowires.
15 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls;
an isolation structure on the top and along the sidewalls of the sub-fin structure;
a vertical arrangement of horizontal nanowires on the isolation structure and vertically over the top surface of the sub-fin structure; and
a gate endcap structure parallel with the vertical arrangement of horizontal nanowires, wherein a portion of the gate endcap structure is continuous with a portion of the isolation structure vertically between the sub-fin structure and the vertical arrangement of horizontal nanowires.
16 . The computing device of claim 15 , further comprising:
a memory coupled to the board.
17 . The computing device of claim 15 , further comprising:
a communication chip coupled to the board.
18 . The computing device of claim 15 , further comprising:
a battery coupled to the board.
19 . The computing device of claim 15 , wherein the component is a packaged integrated circuit die.
20 . The computing device of claim 15 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.