Three-dimensional memory devices and fabricating methods thereof
Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.
1 . A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising an array of first type memory cells;
a second semiconductor structure comprising an array of dynamic flash memory cells different from the first type memory cells;
a third semiconductor structure comprising a first peripheral circuit; and
a fourth semiconductor structure comprising a second peripheral circuit;
wherein the third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.
2 . The 3D memory device of claim 1 , wherein:
the first semiconductor structure further comprises a first semiconductor layer;
the array of first type memory cells comprises an array of NAND memory strings formed on the first semiconductor layer;
the second semiconductor structure further comprises a second semiconductor layer; and
the array of dynamic flash memory cells comprises an array of multi-gate dynamic flash memory (DFM) cells formed on the second semiconductor layer.
3 . The 3D memory device of claim 2 , wherein:
the first peripheral circuit comprises a plurality of first type transistors having a first operating voltage on a first side of a third semiconductor layer; and
the second peripheral circuit comprises a plurality of third type transistors having a third operating voltage on a second side of the third semiconductor layer opposite to the first side of the third semiconductor layer.
4 . The 3D memory device of claim 3 , wherein:
the first peripheral circuit or the second peripheral circuit comprises a plurality of second type transistors having a second operating voltage lower than the first operating voltage and higher than the third operating voltage.
5 . The 3D memory device of claim 4 , further comprising:
a first bonding interface between the first semiconductor structure and the third semiconductor structure; and
a second bonding interface between the second semiconductor structure and the fourth semiconductor structure.
6 . The 3D memory device of claim 5 , wherein:
the first semiconductor structure further comprises a first interconnect layer comprising a first interconnect coupled to the array of NAND memory strings;
the second semiconductor structure further comprises a second interconnect layer comprising a second interconnect coupled to the array of multi-gate DFM cells;
the third semiconductor structure further comprises a third interconnect layer comprising a third interconnect coupled to the first peripheral circuit; and
the fourth semiconductor structure further comprises a fourth interconnect layer comprising a fourth interconnect coupled to the second peripheral circuit.
7 . The 3D memory device of claim 6 , further comprising:
a third through contact penetrating the third semiconductor layer to couple the third interconnect and the fourth interconnect.
8 . The 3D memory device of claim 7 , wherein the first semiconductor structure further comprises:
a first through contact penetrating the first semiconductor layer to couple the first interconnect; and
a first pad-out interconnect layer including a first contact pad in electrical connection with the first through contact.
9 . The 3D memory device of claim 7 , wherein the second semiconductor structure further comprises:
a second through contact penetrating the second semiconductor layer to couple the second interconnect; and
a second pad-out interconnect layer including a second contact pad in electrical connection with the second through contact.
10 . The 3D memory device of claim 2 , wherein:
a semiconductor channel of each NAND memory string comprises a doped region in contact with the first semiconductor layer.
11 . A system, comprising:
a memory device configured to store data, and comprising:
a first semiconductor structure comprising an array of first type memory cells,
a second semiconductor structure comprising an array of dynamic flash memory cells different from the first type memory cells,
a third semiconductor structure comprising a first peripheral circuit, and
a fourth semiconductor structure comprising a second peripheral circuit,
wherein the third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction; and
a memory controller coupled to the memory device and configured to control the array of first type memory cells and the array of dynamic flash memory cells through the first peripheral circuit and the second peripheral circuit.
12 . The system of claim 11 , wherein:
the first semiconductor structure further comprises a first semiconductor layer;
the array of first type memory cells comprises an array of NAND memory strings formed on the first semiconductor layer;
the second semiconductor structure further comprises a second semiconductor layer; and
the array of dynamic flash memory cells comprises an array of multi-gate dynamic flash memory (DFM) cells formed on the second semiconductor layer.
13 . The system of claim 12 , wherein:
the first peripheral circuit comprises a plurality of first type transistors having a first operating voltage on a first side of a third semiconductor layer; and
the second peripheral circuit comprises a plurality of third type transistors having a third operating voltage on a second side of the third semiconductor layer opposite to the first side of the third semiconductor layer.
14 . The system of claim 13 , wherein:
the first peripheral circuit or the second peripheral circuit comprises a plurality of second type transistors having a second operating voltage lower than the first operating voltage and higher than the third operating voltage.
15 . The system of claim 14 , wherein the memory device further comprises:
a first bonding interface between the first semiconductor structure and the third semiconductor structure; and
a second bonding interface between the second semiconductor structure and the fourth semiconductor structure.
16 . The system of claim 15 , wherein:
the first semiconductor structure further comprises a first interconnect layer comprising a first interconnect coupled to the array of NAND memory strings;
the second semiconductor structure further comprises a second interconnect layer comprising a second interconnect coupled to the array of multi-gate DFM cells;
the third semiconductor structure further comprises a third interconnect layer comprising a third interconnect coupled to the first peripheral circuit; and
the fourth semiconductor structure further comprises a fourth interconnect layer comprising a fourth interconnect coupled to the second peripheral circuit.
17 . The system of claim 16 , wherein the memory device further comprises:
a third through contact penetrating the third semiconductor layer to couple the third interconnect and the fourth interconnect.
18 . The system of claim 17 , wherein the first semiconductor structure further comprises:
a first through contact penetrating the first semiconductor layer to couple the first interconnect; and
a first pad-out interconnect layer including a first contact pad in electrical connection with the first through contact.
19 . The system of claim 17 , wherein the second semiconductor structure further comprises:
a second through contact penetrating the second semiconductor layer to couple the second interconnect; and
a second pad-out interconnect layer including a second contact pad in electrical connection with the second through contact.
20 . The system of claim 12 , wherein:
a semiconductor channel of each NAND memory string comprises a doped region in contact with the first semiconductor layer.