Semiconductor device
A semiconductor device according to the present embodiment includes a substrate having a first semiconductor circuit provided thereon. First pads are located on the substrate. A first insulating layer is located on an outer side of each of the first pads. Second pads are respectively bonded to the first pads. A second insulating layer is located on an outer side of each of the second pads and is bonded to the first insulating layer. The first pads each include a first conductive material, and a first insulating material located on an inner side of the first conductive material on a bonding surface of the first pads and the second pads.
1. A semiconductor device comprising:
a substrate having a first semiconductor circuit provided thereon;
first pads located on the substrate;
second pads respectively bonded to the first pads;
a first insulating layer located outside of each of the first pads on a bonding surface of the first pads and the second pads;
and
a second insulating layer located outside of each of the second pads on the bonding surface and bonded to the first insulating layer, wherein
the first pads each comprise a first area including a first conductor and a second area including a third insulating layer on the bonding surface, the second area is located inside of the first area on the bonding surface,
the first semiconductor circuit comprises one of a memory cell array and a CMOS circuit configured to control the memory cell array, and
the device further comprises a second semiconductor circuit comprising the other of the memory cell array and the CMOS circuit configured to control the memory cell array on an opposite side to the first semiconductor circuit with the bonding surface interposed between the first semiconductor circuit and the second semiconductor circuit.
2. The device of claim 1 , wherein the second area comprises a first extending portion extending in a first direction on the bonding surface.
3. The device of claim 1 , wherein the second area is smaller than the first area on the bonding surface.
4. The device of claim 1 , wherein the second pads each comprise a third area including a second conductor and a fourth area including a fourth insulating layer on the bonding surface, the fourth area is located inside of the third area on the bonding surface.
5. The device of claim 4 , wherein the fourth area comprises a second extending portion extending in a second direction lying in an in-plane direction of the bonding surface and different from the first direction on the bonding surface.
6. The device of claim 1 , wherein
on the bonding surface,
the third insulating layer comprises
a first insulating portion,
a second insulating portion arranged alongside of the first insulating portion in the first direction and being closest thereto, and
a third insulating portion arranged alongside of the first insulating portion in a second direction lying in an in-plane direction of the bonding surface and perpendicular to the first direction, and being closest thereto.
7. The device of claim 6 , wherein
on the bonding surface,
the fourth insulating layer comprises
a fourth insulating portion,
a fifth insulating portion arranged alongside of the fourth insulating portion in the first direction and closest thereto, and
a sixth insulating portion arranged alongside of the fourth insulating portion in the second direction and closest thereto, and
when a distance between the first insulating portion and the second insulating portion closest in the first direction is a first distance, and
a distance between the fourth insulating portion and the fifth insulation portion closest in the first direction is a second distance,
the first distance is different from the second distance.
8. The device of claim 1 , wherein the first insulating layer and the third insulating layer are simultaneously formed.
9. The device of claim 1 , wherein
the first insulating layer and the first insulator comprise oxygen and silicon, and
the third insulating layer comprises copper, gold, or copper and gold.
10. A semiconductor device comprising:
a substrate having a first semiconductor circuit provided thereon;
first pads located on the substrate;
second pads respectively bonded to the first pads;
a first insulating layer located outside of each of the first pads on a bonding surface of the first pads and the second pads; and
a second insulating layer located outside of each of the second pads on the bonding surface and bonded to the first insulating layer, wherein
the first pads each comprise a first area including a first conductor and a second area including a third insulating layer on the bonding surface, the second area is located inside of the first area on the bonding surface,
the first semiconductor circuit comprises a first memory cell array and a first CMOS circuit configured to control the first memory cell array, and
the device further comprises a second semiconductor circuit comprising a second memory cell array and a second CMOS circuit configured to control the second memory cell array on an opposite side to the first semiconductor circuit with the bonding surface interposed between the first semiconductor circuit and the second semiconductor circuit.
11. The device of claim 10 , wherein the second area comprises a first extending portion extending in a first direction on the bonding surface.
12. The device of claim 10 , wherein the second area is smaller than the first area on the bonding surface.
13. The device of claim 10 , wherein the second pads each comprise a third area including a second conductor and a fourth area including a fourth insulating layer on the bonding surface, the fourth area is located inside of the third area on the bonding surface.
14. The device of claim 13 , wherein the fourth area comprises a second extending portion extending in a second direction lying in an in-plane direction of the bonding surface and different from the first direction on the bonding surface.
15. The device of claim 10 , wherein
on the bonding surface,
the third insulating layer comprises
a first insulating portion,
a second insulating portion arranged alongside of the first insulating portion in the first direction and being closest thereto, and
a third insulating portion arranged alongside of the first insulating portion in a second direction lying in an in-plane direction of the bonding surface and perpendicular to the first direction, and being closest thereto.
16. The device of claim 15 , wherein
on the bonding surface,
the fourth insulating layer comprises
a fourth insulating portion,
a fifth insulating portion arranged alongside of the fourth insulating portion in the first direction and closest thereto, and
a sixth insulating portion arranged alongside of the fourth insulating portion in the second direction and closest thereto, and
when a distance between the first insulating portion and the second insulating portion closest in the first direction is a first distance, and
a distance between the fourth insulating portion and the fifth insulation portion closest in the first direction is a second distance,
the first distance is different from the second distance.
17. The device of claim 10 , wherein the first insulating layer and the third insulating layer are simultaneously formed.
18. The device of claim 10 , wherein
the first insulating layer and the third insulating layer comprise oxygen and silicon, and
the first conductor comprises copper, gold, or copper and gold.