IP Library Granted Patent US 9,343,498
Granted Patent B2
US 9,343,498 · App. 14/734,240 · Granted May 17, 2016

Semiconductor device, imaging device and semiconductor device manufacturing method

Inventor: Haruhisa Saito (Tokyo, JP)
Assignee: OLYMPUS CORPORATION
H01L27/14634H01L21/48H01L21/50H01L21/78H01L23/48H01L24/11H01L24/13H01L24/16H01L24/27H01L24/83H01L24/89H01L24/92H01L24/94H01L25/0657H01L25/50H01L24/29H01L24/32H01L24/73H01L24/81H01L27/1469H01L27/14636H01L2224/0401H01L2224/05568H01L2224/05624H01L2224/05644H01L2224/08112H01L2224/08135H01L2224/1145H01L2224/1146H01L2224/1148H01L2224/1184H01L2224/11452H01L2224/11472H01L2224/13013H01L2224/13017H01L2224/13082H01L2224/13144H01L2224/13155H01L2224/1411H01L2224/16057H01L2224/16106H01L2224/27416H01L2224/27436H01L2224/2919H01L2224/73104H01L2224/73204H01L2224/8012H01L2224/81193H01L2224/83193H01L2224/83194H01L2224/83855H01L2224/83856H01L2224/83862H01L2224/9211H01L2224/94H01L2225/06513H01L2924/12042
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,343,498
App. No.
14/734,240
Granted
May 17, 2016
Kind
B2
Abstract

A semiconductor device manufacturing method includes a wafer stack manufacturing process and a dicing process. The wafer stack manufacturing process includes: a first wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature higher than a glass transition point of the resin film, manufacturing first holes extending from a surface of the resin film to wirings of the circuits, and providing electrodes electrically connected to the wirings in the first holes to form a first wafer; a second wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature lower than a glass transition point of the resin film, manufacturing second holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the second holes to form a second wafer; and a wafer bonding process.

Claims (11)

1. A semiconductor device manufacturing method comprising:

a wafer stack manufacturing process of manufacturing a wafer stack in which a plurality of wafers comprising circuits and electrodes electrically connected to the circuits are stacked; and

a dicing process of dicing the wafer stack,

wherein the wafer stack manufacturing process comprises:

a first wafer manufacturing process of manufacturing a resin film covering the plurality of circuits and heated to a temperature higher than a glass transition point of the resin film, manufacturing first holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the first holes to form a first wafer;

a second wafer manufacturing process of manufacturing a resin film covering the plurality of circuits and heated to a temperature lower than a glass transition point of the resin film, manufacturing second holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the second holes to form a second wafer; and

a wafer bonding process of causing respective electrode sides of the first wafer and the second wafer to be opposite to each other, bonding the respective resin films together by heating the resin film of the second wafer to a temperature higher than the glass transition point, and bonding the respective electrodes together to form a stack of the first wafer and the second wafer constituting at least a part of the wafer stack.

2. The semiconductor device manufacturing method according to claim 1 ,

wherein, in a cross section including a lamination direction in which the plurality of wafers are stacked, a length of surfaces of the electrodes of the first wafer on a bonding-portion side between the electrodes of the first wafer and the electrodes of the second wafer is shorter than a length of surfaces of the electrodes of the second wafer on the bonding-portion side.

3. The semiconductor device manufacturing method according to claim 1 ,

wherein, when the semiconductor device is viewed in a lamination direction in which the plurality of wafers are stacked, surfaces of the electrodes of the first wafer on a bonding-portion side between the electrodes of the first wafer and the electrodes of the second wafer are formed in edge portions of surfaces of the electrodes of the second wafer on the bonding-portion side.

Assignments (2)
CHANGE OF ADDRESS Recorded Dec 2, 2016
From: OLYMPUS CORPORATION
To: OLYMPUS CORPORATION
Reel/Frame 040818/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2015
From: SAITO, HARUHISA
To: OLYMPUS CORPORATION
Reel/Frame 035809/0420 →
Priority Claims (1)
JP 2012-273661 · Dec 14, 2012 · national
Continuity (2)
Continuation PCTJP2013079844 · Nov 5, 2013
Related Publication 20150270304A1 · Sep 24, 2015