Nonvolatile memory devices having floating gate electrodes with nitrogen-doped layers on portions thereof
Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.
1. A nonvolatile memory device comprising:
a substrate;
a tunnel insulating layer on the substrate;
a floating gate electrode on the tunnel insulating layer having a sidewall including a first portion and a second portion above the first portion;
a first nitrogen doped layer on the second portion of the sidewall wherein the first nitrogen doped layer is not formed on a portion of the first portion of the sidewall;
an intergate dielectric layer on the first nitrogen doped layer, wherein the intergate dielectric layer comprises a bottom oxide layer, a middle dielectric layer, and a top oxide layer, wherein the middle dielectric layer comprises a material with a higher dielectric constant relative to the bottom and top oxide layers;
a control gate electrode on the intergate dielectric layer, wherein the control gate electrode includes a polysilicon layer and a metal silicide layer; and
a trench isolation region being in direct contact with the first portion of the sidewall; and
wherein a majority of an interface between the tunnel insulating layer and the floating gate electrode is free of a nitrogen doped layer.
2. The nonvolatile memory device according to claim 1 , wherein the middle dielectric layer comprises a nitride layer.
3. The nonvolatile memory device according to claim 1 , further comprising a second nitrogen doped layer on the top oxide layer.
4. The nonvolatile memory device according to claim 3 , wherein an uppermost surface of the trench isolation region is higher than a surface of the substrate.
5. The nonvolatile memory device according to claim 1 , wherein the first portion of the sidewall includes a substantially vertical sidewall.
6. The nonvolatile memory device according to claim 1 , wherein the first nitrogen doped layer extends between the floating gate and the intergate dielectric layer.
7. A nonvolatile memory device comprising:
an integrated circuit substrate;
source/drain regions in the substrate;
a tunnel insulating layer on the substrate;
a floating gate on the tunnel insulating layer, wherein the floating gate has an upper surface, sidewalls and a bottom surface;
a nitrogen doped layer on the upper surface and the sidewalls of the floating gate, wherein the nitrogen doped layer is not formed on a portion of the sidewalls and wherein a majority of an interface between the tunnel insulating layer and the floating gate is free of a nitrogen doped layer;
an electrically insulating region partially covering the sidewall of the floating gate and being in contact with the portion of the sidewalls where the nitrogen doped layer is not formed;
an intergate dielectric layer on the nitrogen doped layer, wherein the intergate dielectric layer comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer,
wherein the second dielectric layer has a greater dielectric constant than that of the first and third dielectric layers, and
wherein the first and third dielectric layers comprise an oxide layer; and
a control gate on the intergate dielectric layer.
8. The nonvolatile memory device according to claim 7 , wherein the second dielectric layer comprises a nitride layer.
9. The nonvolatile memory device according to claim 7 , wherein the sidewall of the floating gate covered by the electrically insulating region includes a substantially vertical sidewall.
10. The nonvolatile memory device according to claim 9 , further comprising another nitrogen doped layer on the third dielectric layer.
11. The nonvolatile memory device according to claim 10 , wherein the electrically insulating region is a trench isolation region.
12. The nonvolatile memory device according to claim 11 , wherein the control gate includes a polysilicon and a metal silicide layer.
13. The nonvolatile memory device according to claim 12 , wherein the polysilicon layer is in direct contact with the another nitrogen doped layer.
14. The nonvolatile memory device according to claim 13 , wherein an uppermost surface of the trench isolation region is higher than a surface of the substrate.
15. The nonvolatile memory device according to claim 14 , wherein a part of the floating gate covered by the trench isolation region and a part of the floating gate not covered by the trench isolation region has a different width.