Semiconductor package including heat dissipation structure
Provided are a semiconductor package having a structure maximizing heat dissipation efficiency and a method of manufacturing the same. The semiconductor package includes a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, a plurality of through posts on the first redistribution substrate, around the first semiconductor chip, and a second redistribution substrate located over the first semiconductor chip and the through posts, wherein a top surface of the first semiconductor chip is in contact with a bottom surface of the second redistribution substrate.
1 . A semiconductor package comprising:
a first redistribution substrate;
a first semiconductor chip on the first redistribution substrate, the first semiconductor chip including an integrated circuit;
a plurality of through posts arranged on the first redistribution substrate, around the first semiconductor chip, each of the plurality of through posts being comprised of at least two metal layers arranged in a vertical direction with respect to each other; and
a second redistribution substrate located over the first semiconductor chip and the plurality of through posts, the second redistribution substrate including first contact vias and second contact vias, which are exposed on a bottom surface of the second redistribution substrate,
wherein a top surface of the first semiconductor chip is in contact with the bottom surface of the second redistribution substrate,
wherein the plurality of through posts electrically connect the first redistribution substrate and the second redistribution substrate to each other,
wherein the first contact vias are in contact with top surfaces of the plurality of through posts and are electrically connected to the integrated circuit through the plurality of through posts and the first redistribution substrate, and
wherein the second contact vias are in direct physical contact with the top surface of the first semiconductor chip and are electrically insulated from the integrated circuit.
2 . The semiconductor package of claim 1 , wherein the at least two metal layers comprise a lower copper (Cu) metal layer and an upper nickel (Ni) metal layer.
3 . The semiconductor package of claim 1 , wherein the at least two metal layers comprise an upper metal layer and a lower metal layer,
upper metal layers of at least two of the plurality of through posts have different thicknesses from each other.
4 . The semiconductor package of claim 1 , further comprising a sealing member located between the first redistribution substrate and the second redistribution substrate and sealing the first semiconductor chip,
wherein the plurality of through posts extend through the sealing member.
5 . The semiconductor package of claim 1 , further comprising external connection terminals arranged on a bottom surface of the first redistribution substrate in a fan-out (FO) structure.
6 . The semiconductor package of claim 1 , wherein the first semiconductor chip comprises a logic semiconductor chip comprising logic devices.
7 . The semiconductor package of claim 1 , further comprising at least one second semiconductor chip on the second redistribution substrate.
8 . The semiconductor package of claim 1 , further comprising a high-bandwidth memory (HBM) package arranged on the first redistribution substrate and adjacent to the first semiconductor chip.
9 . A semiconductor package comprising:
a first redistribution substrate;
a semiconductor chip on the first redistribution substrate, the semiconductor chip including an integrated circuit;
a plurality of through posts on the first redistribution substrate, around the semiconductor chip;
a second redistribution substrate located over the semiconductor chip and the plurality of through posts, the second redistribution substrate including first contact vias and second contact vias, which are exposed on a bottom surface of the second redistribution substrate;
a sealing member located between the first redistribution substrate and the second redistribution substrate and sealing the semiconductor chip; and
external connection terminals arranged in a fan-out (FO) structure on a bottom surface of the first redistribution substrate,
wherein a top surface of the semiconductor chip is in contact with the bottom surface of the second redistribution substrate,
wherein the plurality of through posts each comprise at least two metal layers arranged in a vertical direction with respect to each other,
wherein the first contact vias are in contact with top surfaces of the plurality of through posts and are electrically connected to the integrated circuit through the plurality of through posts and the first redistribution substrate, and
wherein the second contact vias are in direct physical contact with the top surface of the semiconductor chip and are electrically insulated from the integrated circuit.
10 . The semiconductor package of claim 9 , wherein the at least two metal layers comprise a lower copper (Cu) metal layer and an upper nickel (Ni) metal layer,
and
Ni metal layers of at least two of the plurality of through posts have different thicknesses from each other.
11 . A semiconductor package comprising:
a first redistribution substrate;
a first semiconductor chip on the first redistribution substrate, the first semiconductor chip including an integrated circuit;
a plurality of through posts arranged on the first redistribution substrate, around the first semiconductor chip, each of the plurality of through posts being comprised of at least two metal layers arranged in a vertical direction with respect to each other;
a second redistribution substrate located over the first semiconductor chip and the plurality of through posts, the second redistribution substrate including first contact vias and second contact vias, which are exposed on a bottom surface of the second redistribution substrate;
at least one second semiconductor chip on the second redistribution substrate; and
external connection terminals arranged in a fan-out (FO) structure on a bottom surface of the first redistribution substrate,
wherein a top surface of the first semiconductor chip is in contact with a bottom surface of the second redistribution substrate,
wherein the plurality of through posts electrically connect the first redistribution substrate and the second redistribution substrate to each other,
wherein the first contact vias are in contact with top surfaces of the plurality of through posts and are electrically connected to the integrated circuit through the plurality of through posts and the first redistribution substrate, and
wherein the second contact vias are in direct physical contact with the top surface of the first semiconductor chip and are electrically insulated from the integrated circuit.
12 . The semiconductor package of claim 11 , wherein the first semiconductor chip comprises a logic semiconductor chip, and
the at least one second semiconductor chip comprises a memory semiconductor chip comprising memory devices.
13 . The semiconductor package of claim 11 , further comprising at least one passive device on the second redistribution substrate.
14 . The semiconductor package of claim 11 , further comprising:
a first sealing member located between the first redistribution substrate and the second redistribution substrate and sealing the first semiconductor chip; and
a second sealing member sealing the at least one second semiconductor chip,
wherein the plurality of through posts extend through the first sealing member.
15 . The semiconductor package of claim 1 , wherein the second redistribution substrate includes redistribution lines extending in a horizontal direction, and
wherein the redistribution lines, the second contact vias, and the first semiconductor chip overlap in the vertical direction.
16 . The semiconductor package of claim 15 , wherein a plurality of redistribution lines are formed in different layers of the second redistribution substrate.