Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material

1. An integrated structure comprising:

a vertically extending opening extending through a stack comprising a plurality of alternating conductive levels and dielectric levels, as well as extending into a first material;

a metal-containing material under the first material;

a channel material extending along an entire vertical length of the opening and into the metal-containing material; and

a tunneling material, a charge-storage material, and a charge-blocking material within the opening and extending along an upper vertical portion of sidewalls of the channel material and along a lower vertical portion of the sidewalls of the channel material, and being absent from along an intermediate vertical portion of the sidewalls of the channel material, wherein:

a second material is in direct physical contact with the sidewalls of the channel material along the intermediate vertical portion of the sidewalls of the channel material; and

a dopant of the second material is out-diffused from the second material to the intermediate vertical portion of the sidewalls of the channel material forming a heavily-doped region of the channel material, wherein an interface between the heavily-doped region of the channel material and a lightly-doped region of the channel material overlaps a vertical face of a select device level above the second material.

2. The integrated structure of claim 1 , wherein the first and second materials are a same composition as one another.

3. The integrated structure of claim 1 , wherein the first and second materials are different compositions relative to one another.

4. The integrated structure of claim 1 , wherein the metal-containing material is in direct contact with the first material.

5. An integrated structure, comprising:

vertically-stacked conductive levels, wherein upper conductive levels of the vertically-stacked conductive levels are memory cell levels and a lower conductive level of the vertically-stacked conductive levels is a select device level;

a conductively-doped semiconductor material under the select device level, wherein the conductively-doped semiconductor material is spaced from the select device level by an insulative region;

a channel material extending vertically along the memory cell levels and the select device level, and extending into the conductively-doped semiconductor material, wherein a bottommost-surface of the channel material is in direct contact with the conductively-doped semiconductor material;

a charge-storage material extending vertically along the channel material between the channel material and the vertically-stacked conductive levels wherein the charge-storage material is absent along at least a portion of a vertical sidewall of the channel material; and

the conductively-doped semiconductor material is directly against the portion of the vertical sidewall of the channel material, wherein a dopant of the conductively-doped semiconductor material is out-diffused from the conductively-doped semiconductor material to the portion of the vertical sidewall of the channel material forming a heavily-doped region of the channel material, wherein an interface between the heavily-doped region of the channel material and a lightly-doped region of the channel material overlaps a vertical face of the select device level.

6. An integrated structure, comprising:

vertically-stacked conductive levels, wherein upper conductive levels of the vertically-stacked conductive levels are memory cell levels and a lower conductive level of the vertically-stacked conductive levels is a select device level;

a source line under the select device level and spaced from the select device level by an insulative region;

a channel material extending vertically along the memory cell levels and the select device level and extending downwardly into the source line, wherein a region of the channel material that extends into the source line is a lower region of the channel material; and

a charge-storage material extending vertically along sidewalls of the channel material between the sidewalls of the channel material and the vertically-stacked conductive levels; wherein:

the charge-storage material is absent from a portion of the sidewalls of the channel material;

the source line is in direct physical contact with the portion of the sidewalls of the channel material; and

a dopant of the source line is out-diffused from the source line to the portion of the sidewalls of the channel material forming a heavily-doped region of the channel material, wherein an interface between the heavily-doped region of the channel material and a lightly-doped region of the channel material overlaps a vertical face of the select device level.

7. The integrated structure of claim 6 , wherein the lower region of the channel material is above a lowest region of the channel material and the charge-storage material is along the lowest region of the channel region.

8. The integrated structure of claim 6 , wherein a bottom portion of the source line is a metal-containing material.

9. The integrated structure of claim 6 , wherein the source line comprises silicon.

10. The integrated structure of claim 6 , wherein the source line comprises germanium.