Integrated structures comprising channel material extending into source material

1. An integrated structure, comprising:

vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level;

a conductively-doped semiconductor material under the select device level, and spaced from the select device level by an insulative region;

a channel material extending vertically along the memory cell levels and the select device level, and extending downwardly into the conductively-doped semiconductor material; a region of the channel material that extends into the conductively-doped semiconductor material being a lower region of the channel material and having a vertical sidewall;

a charge-storage material extending vertically along the channel material and being between the channel material and the vertically-stacked conductive levels;

the charge-storage material not being along at least a portion of the vertical sidewall of said lower region of the channel material; the conductively-doped semiconductor material being directly against said portion of the vertical sidewall of the lower region of the channel material; and

wherein the conductively-doped semiconductor material is a second conductively-doped semiconductor material, and is over and directly against a first conductively-doped semiconductor material; wherein the channel material extends downwardly into the first and second conductively-doped semiconductor materials, and directly contacts both of the first and second conductively-doped semiconductor materials; and wherein the first and second conductively-doped semiconductor materials are compositionally different from one another.

2. The integrated structure of claim 1 including a region of the first conductively-doped semiconductor material between the second conductively-doped semiconductor material and the select device level.

3. An integrated structure, comprising:

vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level;

a conductively-doped semiconductor material under the select device level, and spaced from the select device level by an insulative region;

a channel material extending vertically along the memory cell levels and the select device level, and extending downwardly into the conductively-doped semiconductor material, an elevationally bottommost surface of the channel material being in direct contact with the conductively-doped semiconductor material; a region of the channel material that extends into the conductively-doped semiconductor material being a lower region of the channel material and having a vertical sidewall;

a charge-storage material extending vertically along the channel material and being between the channel material and the vertically-stacked conductive levels;

the charge-storage material not being along at least a portion of the vertical sidewall of said lower region of the channel material; the conductively-doped semiconductor material being directly against said portion of the vertical sidewall of the lower region of the channel material; and

wherein said portion of the vertical sidewall of the lower region of the channel material is above a lowest region of the channel material; and wherein the charge-storage material is along the lowest region.

4. An integrated structure, comprising:

vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level; the vertically-stacked conductive levels being configured as two laterally spaced sets along a cross-section; the sets being a first set and a second set; a conductive pillar being between the first and second sets;

a conductively-doped semiconductor material under the select device levels of the first and second sets; the conductive pillar extending to the conductively-doped semiconductor material and being in electrical contact with the conductively-doped semiconductor material;

a first channel material extending vertically along the memory cell levels and the select device level of the first set, and extending downwardly into the conductively-doped semiconductor material; a region of the first channel material that extends into the conductively-doped semiconductor material being a first lower region of the first channel material and having a first vertical sidewall;

a second channel material extending vertically along the memory cell levels and the select device level of the second set, and extending downwardly into the conductively-doped semiconductor material; a region of the second channel material that extends into the conductively-doped semiconductor material being a second lower region of the second channel material and having a second vertical sidewall;

the conductively-doped semiconductor material being directly against the first and second vertical sidewalls; and

wherein the first and second vertical sidewalls directly against the conductively-doped semiconductor material are above lowest regions of the first and second channel materials; wherein a charge-storage material and a tunneling material are along the lowest regions of the first and second channel materials; wherein the charge-storage material comprises silicon nitride, and wherein the tunneling material comprises one or more oxides.

5. An integrated structure, comprising:

vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level;

a source-structure-material under the select device level, and spaced from the select device level by an insulative region;

a channel material extending vertically along the memory cell levels and the select device level, and extending downwardly into the source-structure-material; a region of the channel material that extends into the source-structure-material being a lower region of the channel material and having a vertical sidewall, the channel material having an elevationally bottommost surface in direct contact with the source-structure material;

a charge-storage material extending vertically along the channel material and being between the channel material and the vertically-stacked conductive levels;

the charge-storage material not being along a portion of the vertical sidewall of said lower region of the channel material;

wherein said portion of the vertical sidewall of the lower region of the channel material is above a lowest region of the channel material; and wherein the charge-storage material is along the lowest region; and

wherein a doped region of the channel material extends along said portion, and only partially vertically overlaps the select device level.

6. The integrated structure of claim 5 further comprising metal-containing material under the source-structure-material and in direct contact with the source-structure-material.

7. The integrated structure of claim 6 wherein the source-structure-material comprises silicon.

8. The integrated structure of claim 6 wherein the source-structure-material comprises germanium.

9. An integrated structure, comprising:

memory cell levels over a select device level;

a source-structure-material under the select device level;

a channel material extending through the memory cell levels and the select device level, and extending downwardly into the source-structure-material; a region of the channel material that extends into the source-structure-material being a lower region of the channel material;

a charge-storage material extending along the channel material and being between the channel material and the memory cell levels; the charge-storage material not being along a segment of said lower region of the channel material;

wherein said segment of the lower region of the channel material is above a lowest portion of the channel material; and wherein the charge-storage material is along vertical sidewalls of the lowest portion, a bottom surface of the lowest portion of the channel material being directly against the source-structure-material; and

wherein a doped region of the channel material extends along said segment, and only partially vertically overlaps the select device level.

10. The integrated structure of claim 9 further comprising metal-containing material under the source-structure-material and in direct contact with the source-structure-material.

11. The integrated structure of claim 10 wherein the lowest portion of the channel material extends into the metal-containing material.

12. The integrated structure of claim 9 wherein the lowest portion of the channel material is within the source-structure-material.