Patent Assignment
Reel/Frame 046084/0955
Supplement No. 8 to Patent Security Agreement
Recorded: 2018-05-07
Pages: 16
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2018-04-24
Assignee
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
1300 THAMES STREET, 4TH FLOOR, BALTIMORE, MARYLAND, 21231
Covered Properties
(117)
Apparatus and Methods Including Source Gates
Analyzing Data Using a Hierarchical Structure
Drain Select Gate Formation Methods and Apparatus
Methods and Related Devices for Operating a Memory Array
Resistance Variable Element Methods and Apparatuses
Memory Device Including Current Generator Plate
Dynamic Reference Voltage Determination
Offset Compensation for Ferroelectric Memory Cell Sensing
Methods and Apparatuses Including an Active Area of a Tap Intersected by a Boundary of a Well
Apparatuses and Methods for Forming Multiple Decks of Memory Cells
Apparatuses and Methods to Control Body Potential in 3D Non-Volatile Memory Operations
Sequential Write and Sequential Write Verify in Memory Device
Switched Interface Stacked-Die Memory Architecture
Methods, Apparatus, and Systems to Repair Memory
Non-Volatile Memory Module Architecture to Support Memory Error Correction
Methods and Apparatuses Including an Asymmetric Assist Device
Methods of Patterning a Target Layer
Semiconductor Device Providing an Output in Response to a Read Command or a Mode-Register Read Command
Phase Change Memory Stack with Treated Sidewalls
Semiconductor Device Performing Row Hammer Refresh Operation
Application:
15/884,192 →
Publication:
US 2019/0237132
Memory Devices, Semiconductor Devices and Related Methods
Packaged Semiconductor Assemblies and Methods for Manufacturing Such Assemblies
Conductive Interconnect Structures Incorporating Negative Thermal Expansion Materials and Associated Systems, Devices, and Methods
Methods of Forming Structures and Methods of Decreasing Defect Density
Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Conductive Structures, Wordlines and Transistors
Memory Arrays
Apparatuses Having Body Connection Lines Coupled with Access Devices
Apparatuses and Methods for Performing Logical Operations Using Sensing Circuitry
Stack Of Horizontally Extending And Vertically Overlapping Features, Methods Of Forming Circuitry Components, And Methods Of Forming An Array Of Memory Cells
Array Of Elevationally-Extending Transistors And A Method Used In Forming An Array Of Elevationally-Extending Transistors
Power Delivery Circuitry
Methods and Systems for Averaging Impedance Calibration
Patent:
10,090,836 →
Application:
15/901,737 →
Stacked Semiconductor Dies with Selective Capillary Under Fill
Apparatuses and Methods for Selective Determination of Data Error Repair
Transistors And Arrays Of Elevationally-Extending Strings Of Memory Cells
Patent:
10,297,611 →
Application:
15/903,307 →
Testing Impedance Adjustment
Multiplication Operations in Memory
Interconnect Structures with Intermetallic Palladium Joints and Associated Systems and Methods
Apparatuses and Methods Including Memory Access in Cross Point Memory
Write Command Overlap Detection
Semiconductor Device Structures Including Stair Step Structures, and Related Semiconductor Devices
Apparatuses and Methods for Data Transfer from Sensing Circuitry to a Controller
Programming Memories with Multi-Level Pass Signal
Methods of Forming Photonic Device Structures and Electronic Devices
Semiconductor Device Having Through-Silicon-via and Methods of Forming the Same
Microelectronic Package Structures Including Redistribution Layers
Methods and Apparatuses for Providing a Program Voltage Responsive to a Voltage Determination
Solid State Lighting Devices with Dielectric Insulation and Methods of Manufacturing
Apparatuses and Methods for Memory Testing and Repair
Identifying Asynchronous Power Loss
Virtual Address Table
Memory Device Including Multiple Gate-Induced Drain Leakage Current Generator Circuits
Methods Of Forming An Array Comprising Pairs Of Vertically Opposed Capacitors And Arrays Comprising Pairs Of Vertically Opposed Capacitors
SILICON CHALCOGENATE PRECURSORS COMPRISING A CHEMICAL FORMULA OF Si(XR1)nR24-n AND METHODS OF FORMING THE SILICON CHALCOGENATE PRECURSORS
Plate Defect Mitigation Techniques
Setting a Default Read Signal Based on Error Correction
Memory Cells, Semiconductor Devices Including the Memory Cells, and Methods of Operation
Methods of Forming Conductive Structures Including Stair Step or Tiered Structures Having Conductive Portions
Methods of Accessing Memory Cells, Methods of Distributing Memory Requests, Systems, and Memory Controllers
Power Management Integrated Circuit with Dual Power Feed
Patent:
10,325,631 →
Application:
15/918,627 →
Memory Including a Selector Switch on a Variable Resistance Memory Cell
Power Management Integrated Circuit with Bleed Circuit Control
Power Management Integrated Circuit Load Switch Driver with Dynamic Biasing
Hardware-Based Power Management Integrated Circuit Register File Write Protection
Power Management Integrated Circuit with In Situ Non-Volatile Programmability
Re-Routing Autonomous Vehicles Using Dynamic Routing and Memory Management
Low Power State Implementation in a Power Management Integrated Circuit
Power Management Integrated Circuit (PMIC) Master/Slave Functionality
Differential Amplifier Schemes for Sensing Memory Cells
Patent:
10,388,361 →
Application:
15/920,171 →
Resource Sharing among Vehicle Applications Connected via a Bus
Methods of Forming Integrated Circuitry
Memory Arrays and Methods of Fabricating Integrated Structures
Systems and Methods for Generating Stagger Delays in Memory Devices
Systems and Methods for Conserving Power in Signal Quality Operations for Memory Devices
Multidimensional Contiguous Memory Allocation
Systems and Methods for Improving Output Signal Quality in Memory Devices
Methods for Isolating Portions of a Loop of Pitch-Multiplied Material and Related Structures
Assemblies Comprising Memory Cells and Select Gates
Structure of Integrated Circuitry and a Method of Forming a Conductive Via
Re-Routing Autonomous Vehicles Using Dynamic Routing and Memory Management for Border Security Purposes
Charge Pumps and Methods of Operating Charge Pumps
Memory Devices and Methods for Managing Error Regions
Personalization of a Vehicle Based on User Settings
Integrated Circuit Constructions Comprising Memory And Methods Used In The Formation Of Integrated Circuitry Comprising Memory
Boosted Channel Programming of Memory
Memory Arrays, and Methods of Forming Memory Arrays
Power Management, Dynamic Routing and Memory Management for Autonomous Driving Vehicles
Apparatus Configured to Program Memory Cells Using an Intermediate Level for Multiple Data States
Hybrid Memory Drives, Computer System, and Related Method for Operating a Multi-Mode Hybrid Drive
Output Impedance Calibration for Signaling
Patent:
10,128,842 →
Application:
15/934,663 →
Apparatus and Methods of Operating Memory for Negative Gate to Body Conditions
Apparatus Providing Simplified Alignment of Optical Fiber in Photonic Integrated Circuits
Packaged Semiconductor Components Having Substantially Rigid Support Members and Methods of Packaging Semiconductor Components
Method for Manufacturing a Semiconductor Device Assembly with Through-Mold Cooling Channel Formed in Encapsulant
Black Box Data Recorder with Artificial Intelligence Processor in Autonomous Driving Vehicle
Application:
15/938,504 →
Publication:
US 2019/0302766
Memory Device Configuration Commands
Methods of Forming Electronic Devices Including Magnetic Cell Core Structures
Buffer Operations in Memory
Wireless Devices and Systems Including Examples of Mixing Coefficient Data Specific to a Processing Mode Selection
Semiconductor Device Assembly with Through-Package Interconnect and Associated Systems, Devices, and Methods
Apparatuses and Methods for Comparing Data Patterns in Memory
Apparatuses and Methods for Partial Bit De-Emphasis
Adaptive Rate Compression Hash Processor
Memory Cells Comprising A Programmable Field Effect Transistor Having A Reversibly Programmable Gate Insulator
Integrated Structures Comprising Channel Material Extending into source material
Configurable Operating Mode Memory Device and Methods of Operation
Apparatuses and Methods for Refresh Control
Through-Core Via
Techniques for Clock Signal Jitter Generation
Patent:
10,373,671 →
Application:
15/948,422 →
Post-Packaging Repair of Redundant Rows
Patent:
10,403,390 →
Application:
15/948,585 →
Memory Arrays
Structure and Methods of Forming the Structure
Compensating for Variations in Selector Threshold Voltages
Magnetoresistive Structures, Semiconductor Devices, and Related Systems
Clock Characteristic Determination
Methods for Acquiring Planar View Stem Images of Device Structures
Application:
62/650,529 →
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Supplement No. 7 to Patent Security Agreement
Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0965 →
Release of Security Interest
Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
Assignment of Assignor's Interest
Sep 14, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP, LLC
Reel/Frame 064901/0011 →