Drain select gate formation methods and apparatus
Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.
1. A method comprising:
forming a gate material above a tiered semiconductor construction that comprises a vertical string of multiple charge storage devices formed across two or more layers of the tiered semiconductor construction and further comprises a layer of gate polysilicon;
forming a dielectric barrier in the gate material;
forming a first isolation barrier above the gate material and the dielectric barrier;
forming a pillar of semiconductor material vertically in the tiered semiconductor construction and the gate material;
forming a drain region above the pillar;
forming a second isolation barrier above the first isolation layer and the drain region cap; and
forming a conductive contact in the second isolation layer, wherein the conductive contact is in electrical contact with the drain region cap,
wherein forming a dielectric barrier in the layer of gate polysilicon includes:
forming a mask layer above the gate material;
etching an opening for the dielectric barrier in the gate material; and
filling at least a portion of the opening with dielectric material to form the dielectric barrier prior to forming the first isolation layer above the gate material,
wherein the dielectric barrier is contained only in the layer of gate polysilicon.
2. The method of claim 1 , wherein forming a pillar includes:
forming a trench in layers of the tiered semiconductor construction, the gate material, and the first isolation layer; and
filling at least a portion of the trench with polysilicon.
3. The method of claim 2 , wherein the filling at least a portion of the trench with polysilicon includes filling the trench with polysilicon to the top surface of the first isolation layer to form the pillar.
4. The method of claim 2 , wherein the filling at least a portion of the trench with polysilicon includes filling a first portion of the trench with a first type of polysilicon to a level below the top surface of the first isolation region and filling a second portion of the trench with a different type of polysilicon to the top surface of the first isolation layer to form a drain region cap as the drain region.
5. The method of claim 2 , wherein forming a pillar includes filling at least a portion of the trench with p-type polysilicon, and wherein forming a drain region includes providing a drain region cap of n-type polysilicon to form a p-n junction between the drain region cap and the pillar.
6. The method of claim 2 , wherein forming a pillar includes filling at least a portion of the trench with n-type polysilicon, and wherein forming a drain includes providing a drain region cap of p-type polysilicon to form an n-p junction between the drain region cap and the pillar.
7. The method of claim 1 , wherein forming the first isolation layer includes forming a layer of nitride as the first isolation layer, and wherein forming the second isolation layer includes forming a first oxide sub-layer above the first isolation layer, a nitride sub-layer above the first oxide sub-layer and forming a second oxide sub-layer above the nitride sub-layer.
8. The method of claim 1 , wherein the forming a gate material above a tiered semiconductor construction includes forming the gate material above a vertical string of multiple charge storage devices included in multiple memory cells formed vertically along the vertical channel.
9. The method of claim 1 , wherein the forming a gate material includes forming a layer of gate polysilicon above the tiered semiconductor construction.
10. The method of claim 9 , wherein the forming a gate material includes forming a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel.
11. The method of claim 9 , wherein the forming a dielectric barrier in the gate material includes forming the dielectric barrier within the layer of polysilicon.
12. The method of claim 10 , wherein the forming a drain region includes forming a drain region of the SGD transistor at an end of the vertical channel and within the first isolation barrier.
13. The method of claim 1 , wherein the forming a pillar of semiconductor material includes forming a vertical semiconductor column in the tiered semiconductor construction and the gate material.
14. The method of claim 1 ,
wherein the forming a gate material above a tiered semiconductor construction includes forming the gate material above a vertical string of multiple charge storage devices included in multiple memory cells formed vertically along the vertical channel,
wherein forming the second isolation layer includes forming the second isolation layer to contact the first isolation layer,
wherein forming the conductive contact includes forming the conductive contact in electrical contact with the drain region of the SGD transistor, and
wherein the multiple memory cells extend vertically from the SGD transistor.