Patent Assignment
Reel/Frame 050709/0965
Release of Security Interest
Recorded: 2019-10-10
Pages: 16
Assignor
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Executed: 2019-07-31
Assignee
MICRON TECHNOLOGY, INC.
8000 S FEDERAL WAY, BOISE, IDAHO, 83707
Covered Properties
(202)
Memory Arrays
Packaged Semiconductor Components Having Substantially Rigid Support Members and Methods of Packaging Semiconductor Components
Packaged Semiconductor Assemblies and Methods for Manufacturing Such Assemblies
Methods for Isolating Portions of a Loop of Pitch-Multiplied Material and Related Structures
Switched Interface Stacked-Die Memory Architecture
Methods, Apparatus, and Systems to Repair Memory
Memory Devices and Methods for Managing Error Regions
Solid State Lighting Devices with Dielectric Insulation and Methods of Manufacturing
Analyzing Data Using a Hierarchical Structure
Methods of Accessing Memory Cells, Methods of Distributing Memory Requests, Systems, and Memory Controllers
Apparatus and Methods Including Source Gates
Stack Of Horizontally Extending And Vertically Overlapping Features, Methods Of Forming Circuitry Components, And Methods Of Forming An Array Of Memory Cells
Memory Devices, Semiconductor Devices and Related Methods
Configurable Operating Mode Memory Device and Methods of Operation
Memory Cells, Semiconductor Devices Including the Memory Cells, and Methods of Operation
Write Command Overlap Detection
Conductive Interconnect Structures Incorporating Negative Thermal Expansion Materials and Associated Systems, Devices, and Methods
Apparatus Providing Simplified Alignment of Optical Fiber in Photonic Integrated Circuits
Semiconductor Device Assembly with Through-Package Interconnect and Associated Systems, Devices, and Methods
Apparatuses and Methods for Memory Testing and Repair
Resistance Variable Element Methods and Apparatuses
Setting a Default Read Signal Based on Error Correction
Magnetoresistive Structures, Semiconductor Devices, and Related Systems
Methods and Apparatuses for Providing a Program Voltage Responsive to a Voltage Determination
Apparatuses and Methods for Performing Logical Operations Using Sensing Circuitry
Methods and Apparatuses Including an Active Area of a Tap Intersected by a Boundary of a Well
Methods of Forming Structures and Methods of Decreasing Defect Density
Charge Pumps and Methods of Operating Charge Pumps
Apparatuses and Methods for Comparing Data Patterns in Memory
Testing Impedance Adjustment
Apparatuses and Methods for Forming Multiple Decks of Memory Cells
Methods of Forming Electronic Devices Including Magnetic Cell Core Structures
Phase Change Memory Stack with Treated Sidewalls
Virtual Address Table
Memory Arrays and Methods of Fabricating Integrated Structures
Method for Manufacturing a Semiconductor Device Assembly with Through-Mold Cooling Channel Formed in Encapsulant
Multidimensional Contiguous Memory Allocation
Multiplication Operations in Memory
Interconnect Structures with Intermetallic Palladium Joints and Associated Systems and Methods
Methods of Forming Photonic Device Structures and Electronic Devices
Sequential Write and Sequential Write Verify in Memory Device
Apparatus Configured to Program Memory Cells Using an Intermediate Level for Multiple Data States
Drain Select Gate Formation Methods and Apparatus
Semiconductor Device Having Through-Silicon-via and Methods of Forming the Same
Offset Compensation for Ferroelectric Memory Cell Sensing
Apparatuses and Methods for Selective Determination of Data Error Repair
Apparatuses and Methods for Data Transfer from Sensing Circuitry to a Controller
Non-Volatile Memory Module Architecture to Support Memory Error Correction
Boosted Channel Programming of Memory
Semiconductor Device Structures Including Stair Step Structures, and Related Semiconductor Devices
Plate Defect Mitigation Techniques
Stacked Semiconductor Dies with Selective Capillary Under Fill
Integrated Structures Comprising Channel Material Extending into source material
Methods of Forming Conductive Structures Including Stair Step or Tiered Structures Having Conductive Portions
Apparatuses and Methods for Refresh Control
Memory Device Configuration Commands
Conductive Structures, Wordlines and Transistors
Power Delivery Circuitry
Compensating for Variations in Selector Threshold Voltages
Dynamic Reference Voltage Determination
SILICON CHALCOGENATE PRECURSORS COMPRISING A CHEMICAL FORMULA OF Si(XR1)nR24-n AND METHODS OF FORMING THE SILICON CHALCOGENATE PRECURSORS
Apparatus and Methods of Operating Memory for Negative Gate to Body Conditions
Memory Device Including Current Generator Plate
Apparatuses Having Body Connection Lines Coupled with Access Devices
Wireless Devices and Systems Including Examples of Mixing Coefficient Data Specific to a Processing Mode Selection
Memory Device Including Multiple Gate-Induced Drain Leakage Current Generator Circuits
Array Of Elevationally-Extending Transistors And A Method Used In Forming An Array Of Elevationally-Extending Transistors
Memory Cells Comprising A Programmable Field Effect Transistor Having A Reversibly Programmable Gate Insulator
Structure of Integrated Circuitry and a Method of Forming a Conductive Via
Hybrid Memory Drives, Computer System, and Related Method for Operating a Multi-Mode Hybrid Drive
Apparatuses and Methods for Partial Bit De-Emphasis
Identifying Asynchronous Power Loss
Methods Of Forming An Array Comprising Pairs Of Vertically Opposed Capacitors And Arrays Comprising Pairs Of Vertically Opposed Capacitors
Through-Core Via
Assemblies Comprising Memory Cells and Select Gates
Methods and Systems for Averaging Impedance Calibration
Patent:
10,090,836 →
Application:
15/901,737 →
Transistors And Arrays Of Elevationally-Extending Strings Of Memory Cells
Patent:
10,297,611 →
Application:
15/903,307 →
Memory Arrays, and Methods of Forming Memory Arrays
Memory Arrays
Pseudo-Non-Volatile Memory Cells
Application:
62/641,057 →
Systems and Methods for Generating Stagger Delays in Memory Devices
Finer Grain Dynamic Random Access Memory (Dram)
Application:
62/518,575 →
Systems and Methods for Improving Output Signal Quality in Memory Devices
Systems and Methods for Conserving Power in Signal Quality Operations for Memory Devices
Methods for Acquiring Planar View Stem Images of Device Structures
Application:
62/650,529 →
Differential Amplifier Schemes for Sensing Memory Cells
Patent:
10,388,361 →
Application:
15/920,171 →
Generating and Using Invertible, Shortened Bose-Chaudhuri-Hocquenghem Codewords
Application:
62/628,821 →
Integrated Circuit Constructions Comprising Memory And Methods Used In The Formation Of Integrated Circuitry Comprising Memory
Post-Packaging Repair of Redundant Rows
Patent:
10,403,390 →
Application:
15/948,585 →
Semiconductor Device Providing an Output in Response to a Read Command or a Mode-Register Read Command
Mitigating a Stable Threshold Voltage of a Memory Cell at a Storage System
Application:
62/628,198 →
Techniques for Clock Signal Jitter Generation
Patent:
10,373,671 →
Application:
15/948,422 →
Mitigating an Undetectable Error When Retrieving Critical Data During Error Handling
Application:
62/628,203 →
Semiconductor Device Performing Row Hammer Refresh Operation
Application:
15/884,192 →
Publication:
US US20190237132A1
Background Stable Threshold Voltage Mitigation of a Memory Cell at a Storage System
Application:
62/628,682 →
Providing Data to a New Memory Cell at a Storage System Based on an Unsuccessful Error Correction Operation
Application:
62/628,706 →
Power Management Integrated Circuit (PMIC) Master/Slave Functionality
Power Management Integrated Circuit with Dual Power Feed
Patent:
10,325,631 →
Application:
15/918,627 →
Power Management Integrated Circuit with Bleed Circuit Control
Low Power State Implementation in a Power Management Integrated Circuit
Power Management Integrated Circuit Load Switch Driver with Dynamic Biasing
Hardware-Based Power Management Integrated Circuit Register File Write Protection
Power Management Integrated Circuit with In Situ Non-Volatile Programmability
Storage Backed Memory Package Save Trigger
Application:
62/627,988 →
Firmware Update in a Storage Backed Memory Package
Application:
62/627,969 →
Status Management in Storage Backed Memory Package
Application:
62/627,949 →
Key Encryption Handling
Application:
62/628,123 →
Host Timeout Csave
Application:
62/628,040 →
Partial Save of Memory
Application:
62/628,157 →
Self Refresh Retry
Application:
62/628,089 →
Black Box Data Recorder with Artificial Intelligence Processor in Autonomous Driving Vehicle
Application:
15/938,504 →
Publication:
US US20190302766A1
Methods of Forming Integrated Circuitry
Clock Characteristic Determination
Re-Routing Autonomous Vehicles Using Dynamic Routing and Memory Management
Power Management, Dynamic Routing and Memory Management for Autonomous Driving Vehicles
Re-Routing Autonomous Vehicles Using Dynamic Routing and Memory Management for Border Security Purposes
Output Impedance Calibration for Signaling
Patent:
10,128,842 →
Application:
15/934,663 →
Resource Sharing among Vehicle Applications Connected via a Bus
Health Characteristics of a Memory Device
Application:
62/644,925 →
Self Refresh Bypass
Application:
62/628,135 →
Predictive Data Orchestration in Two Tier Memory Systems
Application:
62/626,347 →
Architecture for Storage Devices Using Embedded Media Controllers
Application:
62/626,527 →
Prioritized Memory Storage Based on Data Stream Characteristics
Application:
62/626,544 →
Input/Output (IO) Acceleration with Message Passing Interface (MPI) Semantics with Persistent Memory
Application:
62/626,419 →
Synchronous Memory Bus Access to Storage Media and Dram Using an SRAM Buffer
Application:
62/626,577 →
CPU Cache Flushing to Persistent Memory with Reduced Instructions
Application:
62/626,565 →
Memory Virtualization for Two Tier Memory Systems
Application:
62/626,491 →
Remote Direct Memory Access (RDMA) in Two Tier Memory Systems
Application:
62/626,523 →
Artificial Neural Network Integrity Verification
Application:
62/636,214 →
DDR5 Memory Device
Application:
62/631,760 →
Optimization of Communication and Data Access in Systems having Persistent Data Storage Devices
Application:
62/629,628 →
Personalization of a Vehicle Based on User Settings
Interface For Data Communication Between Chiplets on an Interposer of a System On A Chip (SOC)
Application:
62/625,520 →
Memory Devices Configured to Provide External Regulated Voltages
Application:
62/635,429 →
Nand Data Placement Schema
Application:
62/644,248 →
Clustered Parity for Nand Data Placement Schema
Application:
62/644,282 →
Structure and Methods of Forming the Structure
Methods and Apparatuses Including an Asymmetric Assist Device
Programming Memories with Multi-Level Pass Signal
Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Buffer Operations in Memory
Apparatuses and Methods Including Memory Access in Cross Point Memory
Apparatuses and Methods to Control Body Potential in 3D Non-Volatile Memory Operations
Microelectronic Package Structures Including Redistribution Layers
Methods of Patterning a Target Layer
Memory Including a Selector Switch on a Variable Resistance Memory Cell
Methods and Related Devices for Operating a Memory Array
Adaptive Rate Compression Hash Processor
Stacked Semiconductor Die Assemblies with Die Substrate Extensions
PCT:
PCT/US2018/018805 ↗
Memory Array Page Table Walk
PCT:
PCT/US2018/017901 ↗
Pre-Writing Memory Cells of an Array
PCT:
PCT/US2018/016048 ↗
Apparatuses Having Body Connection Lines Coupled with Access Devices
PCT:
PCT/US2018/018059 ↗
Wireless Devices and Systems Including Examples of Full Duplex Transmission
PCT:
PCT/US2018/020177 ↗
Obfuscation-Enhanced Memory Encryption
PCT:
PCT/US2018/019830 ↗
Apparatuses Comprising Semiconductor Dies in Face-to-Face Arrangements
PCT:
PCT/US2018/025734 ↗
Semiconductor Devices with Back-Side Coils for Wireless Signal and Power Coupling
PCT:
PCT/US2018/026239 ↗
Semiconductor Devices with Through-Substrate Coils for Wireless Signal and Power Coupling
PCT:
PCT/US2018/026253 ↗
Apparatus and Methods for in Data Path Compute Operations
PCT:
PCT/US2018/021931 ↗
Efficient Utilization of Memory Die Area
PCT:
PCT/US2018/017204 ↗
Semiconductor Device Assemblies with Electrically Functional Heat Transfer Structures
PCT:
PCT/US2018/015661 ↗
Self-Reference for Ferroelectric Memory
PCT:
PCT/US2018/018366 ↗
Garbage Collection
PCT:
PCT/US2018/022804 ↗
Operation of Mixed Mode Blocks
PCT:
PCT/US2018/022587 ↗
Memory Management
PCT:
PCT/US2018/024722 ↗
Inductors with Through-Substrate via Cores
PCT:
PCT/US2018/026256 ↗
Memory Arrays, and Methods of Forming Memory Arrays
PCT:
PCT/US2018/016468 ↗
Multiple Plate Line Architecture for Multideck Memory Array
PCT:
PCT/US2018/021807 ↗
Tiered Error Correction Code (Ecc) Operations in Memory
PCT:
PCT/US2018/021639 ↗
Integrated Structures, Nand Memory Arrays, and Methods of Forming Integrated Structures
PCT:
PCT/US2018/015962 ↗
Methods of Sketch-Based Memory Management and Memory Devices Utilizing the Same
PCT:
PCT/US2018/022188 ↗
Systems and Methods for Array Reset Mode Operation
PCT:
PCT/US2018/026763 ↗
Apparatuses and Methods for Compute in Data Path
PCT:
PCT/US2018/018145 ↗
Methods of Bit-Flagged Sketch-Based Memory Management and Memory Devices Utilizing the Same
PCT:
PCT/US2018/022180 ↗
Nand Memory Arrays, and Methods of Forming Nand Memory Arrays
PCT:
PCT/US2018/016144 ↗
Selective Error Rate Information for Multidimensional Memory
PCT:
PCT/US2018/023227 ↗
Memory Cells and Integrated Structures
PCT:
PCT/US2018/018390 ↗
Apparatuses and Methods for in-Memory Operations
PCT:
PCT/US2018/022802 ↗
Apparatuses and Methods for in-Memory Operations
PCT:
PCT/US2018/018290 ↗
Apparatuses and Methods for in-Memory Data Switching Networks
PCT:
PCT/US2018/021683 ↗
Error Correction Code (Ecc) Operations in Memory for Providing Redundant Error Correction
PCT:
PCT/US2018/021928 ↗
Memory Protection Based on System State
PCT:
PCT/US2018/024064 ↗
Wireless Devices and Systems Including Examples of Configuration Modes for Baseband Units and Remote Radio Heads
PCT:
PCT/US2018/020306 ↗
Semiconductor Devices Having Discretely Located Passivation Material, and Associated Systems and Methods
PCT:
PCT/US2018/022565 ↗
Transaction Identification
PCT:
PCT/US2018/018106 ↗
Kvs Tree
PCT:
PCT/US2018/016892 ↗
Merge Tree Garbage Metrics
PCT:
PCT/US2018/016906 ↗
Merge Tree Modifications for Maintenance Operations
PCT:
PCT/US2018/017043 ↗
Stream Selection for Multi-Stream Storage Devices
PCT:
PCT/US2018/017056 ↗
Apparatuses and Methods for Operating Neural Networks
PCT:
PCT/US2018/021936 ↗
Apparatuses and Methods for Configurable Command and Data Input Circuits for Semiconductor Memories
PCT:
PCT/US2018/025468 ↗
Three Dinemsional Memory Array
PCT:
PCT/US2018/021948 ↗
Methods and Apparatuses for Determining Real-Time Location Information of Rfid Devices
PCT:
PCT/US2018/018767 ↗
Methods and Apparatuses for Processing Multiple Communications Signals with a Single Integrated Circuit Chip
PCT:
PCT/US2018/018807 ↗
Methods of Forming Semiconductor Device Structures Including Linear Structures Substantially Aligned with Other Structures
PCT:
PCT/US2018/020646 ↗
Memory Protocol with Programmable Buffer and Cache Size
PCT:
PCT/US2018/018124 ↗
Arrays of Elevationally-Extending Strings of Memory Cells and Methods of Forming Memory Arrays
PCT:
PCT/US2018/025716 ↗
Memory Devices and Methods Which May Facilitate Tensor Memory Access
PCT:
PCT/US2018/025660 ↗
Apparatus and Method to Switch Configurable Logic Units
PCT:
PCT/US2018/025675 ↗
Secure Memory Arrangements
PCT:
PCT/US2018/024084 ↗
Multi-Die Inductors with Coupled Through-Substrate via Cores
PCT:
PCT/US2018/026263 ↗
3D Interconnect Multi-Die Inductors with Through-Substrate via Cores
PCT:
PCT/US2018/026269 ↗
Method and Apparatus for Precharge and Refresh Control
PCT:
PCT/US2018/025533 ↗
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Feb 27, 2018
From: PALMER, DAVID A.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045051/0201 →
Assignment of Assignor's Interest
Mar 2, 2018
From: SCOTT D. SCHELLHAMMER
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045091/0630 →
Assignment of Assignor's Interest
Mar 28, 2018
From: SCHWAB, MATT E.; BROOKS, J. MICHAEL; CORISIS, DAVID J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045372/0846 →
Supplement No. 8 to Patent Security Agreement
May 7, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 046084/0955 →
Assignment of Assignor's Interest
Jun 25, 2018
From: KALAVADE, PRANAV; RAJWADE, SHANTANU R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046196/0633 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →