Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator
View Patent ↗A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V t 's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.
1. A memory cell, comprising:
an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V t 's of the programmable transistor, the programmable transistor comprising a top source/drain region and a bottom source/drain region;
a bottom select device electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor;
a top select device electrically coupled in series with and elevationally outward of the top source/drain region of the programmable transistor;
a bottom select line electrically coupled in series with and elevationally inward of the bottom select device;
a top select line electrically coupled in series with and elevationally outward of the top select device
the bottom select device and the top select device being the same type electrical component, the type of electrical component being a field effect transistor; and
the programmable transistor having a conductive gate and a channel region, the conductive gate not completely encircling the channel region, a conductive electrode directly against the channel region at a circumferential location where the conductive gate is not encircling over the channel region.
2. The memory cell of claim 1 wherein the electrode extends to be directly against only one of the top source/drain region or the bottom source/drain region of the programmable transistor.
3. The memory cell of claim 2 wherein the one of the top source/drain region or the bottom source/drain region to which the electrode extends is a shared source/drain region, the top or bottom select device most proximate the extending electrode comprising a field effect transistor, the shared source/drain region being shared by the programmable transistor and the field effect transistor of the top or bottom select device.
4. The memory cell of claim 1 wherein the electrode does not extend to be directly against either of the top source/drain region or the bottom source/drain region of the programmable transistor.