SEMICONDUCTOR DEVICE PERFORMING ROW HAMMER REFRESH OPERATION

1 . An apparatus comprising:

a memory cell array including a normal memory region and a redundancy memory region, a plurality of row addresses in the normal memory region being defined, at least in past, with a first value of a redundant signal, and a plurality of row addresses in the redundant memory region being defined, at least in part, with a second value of the redundant signal;

a first circuit configured to receive a row address signal produce the first value of the redundant signal if the first circuit detects that the row address signal is inconsistent to any of redundancy information, and produce the second value of the redundant signal and an additional row address signal if the first circuit detects that the row address signal is consistent to any of the redundancy information; and

a second circuit configured to produce further additional row address signal based on the row address signal and the first value of the redundant signal or based on the additional row address signal and the second value of the redundant signal.

2 . The apparatus of claim 1 , further comprising a third circuit configured to access the normal memory region based on the row address signal with the first value of the redundant signal, and to access the redundancy memory region based on the additional row address signal with the second value of the redundant signal.

3 . The apparatus of claim 2 , wherein the third circuit is configured to access the normal memory region based on the further additional row address signal with the first value of the redundant signal.

4 . The apparatus of claim 3 , wherein the third circuit is configured to access the redundancy memory region based an the further additional row address signal with the second value of the redundant signal.

5 . The apparatus of claim 1 ,

wherein the normal memory region includes first and second word lines physically adjacent to each other,

wherein the first word line is accessed based on the row address signal with the first value of the redundant signal, and

wherein the second word line is accessed based on the further additional row address signal generated based on the row address signal with the first value of the redundant signal.

6 . The apparatus of claim 5 ,

wherein the redundancy memory region includes third and fourth word lines physically adjacent to each other,

wherein the third word line is accessed based on the additional row address signal with the second value of the redundant signal, and

wherein the fourth word line is accessed based on the further additional row address signal generated based on the further additional row address signal with the second value of the redundant signal.

7 . The apparatus of claim 6 ,

wherein the normal memory region further includes a fifth word line, and

the redundancy memory region further includes a sixth word line physically adjacent to the fifth word line.

8 . The apparatus of claim 7 , wherein the second circuit is configured to produce the further additional row address signal with the second value of the redundant signal related to the sixth word line based on the row address signal with the first value of the redundant signal related to the fifth word line.

9 . The apparatus of claim 1 , wherein the second circuit is configured to produce the further additional row address signal with the first value of the redundant signal related to the fifth word line based on the row address signal with the second value of the redundant signal related to the sixth word line.

10 . The apparatus of claim 1 , wherein the second circuit is configured to produce the further additional row address signal by incrementing or decrementing the row address signal with the first value of the redundant signal or the additional row address signal with the second value of the redundant signal

11 . An apparatus comprising:

an address terminal configured to receive an input address;

an address storing circuit configured to store a defective address;

an address comparator configured to activate a hit signal when the input address matches with the defective address;

an address converter configured to convert the input address into a spare address when the hit signal is in an active state; and

an address calculator configured to generate a refresh address based on the hit signal and a selected one of the input address and the spare address.

12 . The apparatus of claim 11 , wherein the address comparator is configured to receive the refresh address instead of the input address when a control signal is activated.

13 . The apparatus of claim 12 , wherein the address comparator is configured to stop a comparing operation so as not to activate the hit signal when the control signal is activated.

14 . An apparatus comprising:

a first memory cell array configured to be assigned with normal addresses;

a second memory cell array configured to be assigned with spare addresses;

an address storing circuit configured to store a defective address included in the normal addresses;

an address comparator configured to activate a hit signal when an input address supplied to an address input node matches with the defective address;

an address selector configured to select the input address when the hit signal is in an inactive state, and select one of the spare addresses when the hit signal is in an active state; and

an address calculator configured to generate a first refresh address based on a selected one of the input address and the one of the spare addresses,

wherein the first refresh address is supplied to the address input node of the address comparator when a first refresh signal is activated, and

wherein the address comparator is configured to stop a comparing operation so as not to activate the hit signal when the first refresh signal is activated.

15 . The apparatus of claim 14 , wherein the address calculator is configured to generate the first refresh address using the hit signal.

16 . The apparatus of claim 15 , wherein the hit signal is a most significant bit of the first refresh address.

17 . The apparatus of claim 14 , wherein the address input node of the address comparator is supplied with a second refresh address when a second refresh signal is activated.

18 . The apparatus of claim 17 , wherein the first and second refresh signals are exclusively activated.

19 . The apparatus of claim 18 , wherein the address comparator is configured to perform the comparing operation so as to be able to activate the hit signal when the second refresh signal is activated.

20 . The apparatus of claim further comprising a command control circuit configured to activate one of the first and second refresh signals in response to a refresh command issued from an outside of the apparatus.