Memory device including multiple gate-induced drain leakage current generator circuits
Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.
1. An apparatus comprising:
a substrate;
a conductive material located over the substrate;
a pillar contacting the conductive material and having a length extending between the first conductive material and the substrate;
memory cells and control lines located along the pillar and between the conductive material and the substrate;
a first select gate and a first select line located along the pillar and between the conductive material and the memory cells;
a second select gate and a second select line located along the pillar and between the first conductive material and the first select line;
a first additional conductive material located along the pillar and between the conductive material and the second select line; and
a second additional conductive material located along the pillar and between the conductive material and the first additional conductive material, wherein the pillar includes a conductive portion and a dielectric portion, the conductive portion contacts the dielectric portion at an interface, and the interface is located at a level between levels of the first select line and the second additional conductive material.
2. The apparatus of claim 1 , further comprising a data line, wherein the conductive material is part of the data.
3. The apparatus of claim 1 , wherein the conductive portion of the pillar includes polycrystalline silicon.
4. The apparatus of claim 1 , wherein the conductive portion of the pillar includes n-type material.
5. The apparatus of claim 1 , wherein each of the memory cells includes a structure configured to store information, and the structure is polycrystalline silicon structure.
6. The apparatus of claim 1 , wherein each of the memory cells includes a structure configured to store information and the structure is a dielectric structure.
7. The apparatus of claim 1 , wherein the memory cells, and the first and second select gates have a same structure.
8. The apparatus of claim 1 , wherein the control lines and the first and d select lines are separated from a conductive channel of the pillar by a same distance.
9. The apparatus of claim 1 , wherein the control lines, the first and second select lines, and first and second additional conductive materials include a same material.
10. The apparatus of claim 1 , wherein a material of each of the control lines is metal.
11. An apparatus comprising.
a substrate;
a conductive material located over the substrate;
a pillar contacting the conductive material;
memory cells and control lines located along the pillar, the conductive material located between the memory cells and the substrate;
a first select gate and a first select line located along the pillar and between the memory cells and the conductive material;
a second select gate and a second select line located along the pillar and between the first select line and the conductive material;
a first additional conductive material located along the pillar and between the second select line and the conductive material; and
a second additional material located along the pillar and between the first additional conductive material and the conductive material, wherein the pillar includes a first conductive portion and a second conductive portion, the first conductive portion contacts the second conductive portion at an interface, and the interface is located at a level between levels of the first select line and the second additional conductive material.
12. The apparatus of claim 11 , further comprising a source line, wherein the conductive material is part of the source.
13. The apparatus of claim 11 , wherein at least one of the first and second the conductive portions of the pillar includes polycrystalline silicon.
14. The apparatus of claim 11 , wherein each of the memory cells includes a structure configured to store information, and the structure is polycrystalline silicon structure.
15. The apparatus of claim 11 , wherein each of the memory cells includes a structure configured to store information, and the structure is a dielectric structure.
16. An apparatus comprising:
a first conductive material located in a first level of the apparatus;
a second conductive material located in a second level of the apparatus;
a pillar including a length extending between the first and second levels and contacting the first and second conductive materials;
memory cells and control lines located along the pillar and between the first and second conductive materials;
a first select gate and a first select line located along the pillar between the first conductive material and the memory cells;
a second select gate and a second select line located along the pillar and between the first conductive material and the first select line:
a first additional conductive material located along the pillar and between the first conductive material and the second select line;
a second additional conductive material located along the pillar and between the first conductive material and the first additional conductive material, wherein the pillar includes a conductive portion and a dielectric portion, the conductive portion contacts the dielectric portion at a first interface, and the first interface is located at a level between levels of the first select line and the second additional conductive material;
a third select gate and a third select line located along the pillar and between the memory cells and the second conductive material;
a fourth select gate and a fourth select line located along the pillar and between the third line and the second conductive material;
a third additional conductive material located along the pillar and between the fourth select line and the second conductive material; and
a fourth additional material located along the pillar and between the third additional conductive material and the second conductive material, wherein the pillar includes a first additional conductive portion and a second additional conductive portion, the first additional conductive portion contacts the second additional conductive portion at a second interface, and the second interface is located at a level between levels of the third select line and the fourth additional conductive material.
17. The apparatus of claim 16 , further comprising a data line and a source, wherein the first conductive material is part of the data line, and the second conductive material is part of the source.
18. The apparatus of claim 16 , wherein the first conductive portion of the pillar includes polycrystalline silicon.
19. The apparatus of claim 18 , wherein the second conductive portion of the pillar includes polycrystalline silicon.
20. The apparatus of claim 16 , wherein the control lines, the first, second, third, and fourth select lines, and the first, second, third, and fourth additional conductive materials are separated from a conductive channel of the pillar by a same distance.