Methods, apparatus, and systems to repair memory
View Patent ↗Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag fields indicating a type of row/column repair to be performed for at least a portion of a row/column of memory cells, and a second plurality of tag fields to indicate a location of memory cells used to perform the row/column repair.
1. A method comprising:
determining a first repair type for at least one row of memory cells of a memory device using a first field in a tag random access memory (RAM) in a repair controller; and
when the first repair type is determined to be a partial row repair,
identifying at least one bad column address for at least one defective cell in the at least one row of memory cells of the memory device,
accessing an auxiliary data RAM in the repair controller to retrieve first data for the at least one defective cell in the at least one row of memory cells of the memory device, and
accessing the memory device to retrieve second data for non-defective cells in the at least one row of memory cells of the memory device.
2. The method of claim 1 , further comprising comparing the at least one bad column address with a column address received from a memory controller.
3. The method of claim 1 , wherein the bad column address is compared with an address from the tag RAM to generate a control signal to instruct a selector to select data based on a second field in the tag RAM from either a redundant block in the memory device or an auxiliary data RAM in the repair controller.
4. The method of claim 1 , wherein when a second repair type is determined to comprise a complete row repair for at least a second row of memory cells, the complete repair is performed for at least the second row of memory cells of the memory device using data from a redundant block in the memory device.
5. The method of claim 1 , wherein the at least one bad column address for the at least one defective cell in the at least one row of memory cells of the memory device is identified by a second field of the tag RAM.
6. The method of claim 1 , wherein accessing the auxiliary data RAM in the repair controller comprises reading the auxiliary data RAM in the repair controller, and wherein accessing the memory device comprises reading the memory device.
7. The method of claim 1 , wherein accessing the auxiliary data RAM in the repair controller comprises writing the first data into the auxiliary data RAM, and wherein accessing the memory device comprises writing the second data into the memory device.
8. A method comprising:
determining a first repair type for at least one row of memory cells of a memory device using a first field in a tag random access memory (RAM) in a repair controller; and
when the first repair type is determined to be a partial row repair,
identifying at least one bad column address for at least one defective cell in the at least one row of memory cells of the memory device,
accessing a redundant memory in the memory device to retrieve first data for the at least one defective cell in the at least one row of memory cells of the memory device, and
accessing the memory device to retrieve second data for non-defective cells in the at least one row of memory cells of the memory device.
9. The method of claim 8 , further comprising comparing the at least one bad column address with a column address received from a memory controller.
10. The method of claim 8 , wherein the at least one bad column address for the at least one defective cell in the at least one row of memory cells of the memory device is identified by a second field of the tag RAM.
11. The method of claim 1 , wherein when a second repair type is determined to comprise a complete row repair for at least a second row of memory cells, the complete repair is performed for at least the second row of memory cells of the memory device using data from a redundant block in the memory device.
12. The method of claim 8 , wherein accessing the redundant memory in the memory device comprises reading the redundant memory in the memory device.
13. The method of claim 8 , wherein accessing the redundant memory in the memory device comprises writing the first data into the redundant memory in the memory device.