Identifying asynchronous power loss

1. An apparatus, comprising:

an array of memory cells; and

a controller to perform access operations on the array of memory cells;

wherein the controller is configured to:

iteratively program a group of memory cells of the array of memory cells to respective desired data states as part of a programming operation on the array of memory cells;

determine whether a power loss to the apparatus from the power supply is indicated while iteratively programming the group of memory cells to the respective desired data states; and

if a power loss to the apparatus is indicated while iteratively programming the group of memory cells to the respective desired data states, change the desired data state of a particular memory cell of the group of memory cells before continuing with iteratively programming the group of memory cells to the respective desired data states.

2. The apparatus of claim 1 , wherein the controller is further configured to:

inhibit the particular memory cell from programming until determining that power to the apparatus is lost while iteratively programming the group of memory cells to the respective desired data states; and

enable the particular memory cell for programming in response to changing the desired data state of the particular memory cell.

3. The apparatus of claim 1 , wherein the controller, in changing the desired data state of the particular memory cell, is further configured to change the desired data state of the particular memory cell from a data state corresponding to a particular range of threshold voltage to a data state corresponding to a higher range of threshold voltages.

4. The apparatus of claim 1 , wherein the controller, in determining whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells to the respective desired data states, is further configured to determine whether a logic level of a control signal changes while iteratively programming the group of memory cells to the respective desired data states.

5. The apparatus of claim 4 , wherein the controller, in determining whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells to the respective desired data states, is further configured to determine periodically whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells to the respective desired data states.

6. The apparatus of claim 5 , wherein the controller, in determining periodically whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells to the respective desired data states, is further configured to determine whether a power loss to the apparatus is indicated once for each iteration of iteratively programming the group of memory cells to the respective desired data states.

7. The apparatus of claim 1 , wherein the controller, in iteratively programming the group of memory cells to the respective desired data states, is further configured to:

inhibit any memory cell of the group of memory cells having its desired data state from programming;

apply a programming pulse to each memory cell of the group of memory cells;

verify whether memory cells of the group of memory cells have attained their respective desired data states;

determine whether programming is complete; and

if programming is not complete:

inhibit any memory cell of the group of memory cells attaining its desired data state from further programming; and

change a voltage level for programming pulses before applying a next programming pulse to each memory cell of the group off memory cells.

8. The apparatus of claim 7 , wherein the controller is further configured to:

determine whether a power loss to the apparatus is indicated after determining whether programming is complete and before inhibiting any memory cell of the group of memory cells attaining its desired data state from further programming if programming is not complete; and

change the desired data state of the particular memory cell after determining that a power loss to the apparatus is indicated and before changing the voltage level for the programming pulses.

9. The apparatus of claim 1 , wherein the group of memory cells is a page of memory cells of the array of memory cells, the apparatus further comprising:

an energy storage device configured to store energy from a power supply;

wherein the controller configured to continue with iteratively programming the page of memory cells to the respective desired data states comprises the controller being configured to continue with iteratively programming the page of memory cells to the respective desired data states while receiving power from the energy storage device.

10. The apparatus of claim 9 , wherein the energy storage device is selected from a group consisting of a capacitance and a battery.

11. The apparatus of claim 9 , wherein the page of memory cells is a last written page of memory cells of a block of memory cells, and wherein the controller is further configured to:

read a data state of the particular memory cell of the last written page of memory cells;

determine whether the data state of the particular memory cell is a particular data state; and

mark the last written page of memory cells as affected by power loss from the power supply during the programming operation of the last written page of memory cells if the data state of the particular memory cell is not the particular data state.

12. An apparatus, comprising:

an array of memory cells;

a controller to perform access operations on the array of memory cells; and

an energy storage device configured to store energy from a power supply;

wherein the controller is configured to:

iteratively program a group of memory cells to respective interim desired data states;

iteratively program the group of memory cells to respective subsequent desired data states after iteratively programming the group of memory cells to the respective interim desired data states,

determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells to the respective subsequent desired data states; and

if a power loss to the apparatus is indicated while iteratively programming the group of memory cells to the respective subsequent desired data states:

change the subsequent desired data state of a particular memory cell of the group of memory cells before continuing with iteratively programming the group of memory cells to the respective subsequent desired data states.

13. The apparatus of claim 12 , wherein the controller configured to iteratively program the group of memory cells to the respective interim desired data states comprises the controller being configured to perform a first pass of a programming operation on the array of memory cells, and wherein the controller configured to iteratively program the group of memory cells to the respective subsequent desired data states comprises the controller being configured to perform a second pass of the programming operation on the array of memory cells.

14. The apparatus of claim 12 , wherein the controller configured to iteratively program the group of memory cells to the respective interim desired data states comprises the controller being configured to program two digits of data to the group of memory cells, and wherein the controller configured to iteratively program the group of memory cells to the respective subsequent desired data states comprises the controller being configured to program a third digit of data to the group of memory cells.

15. The apparatus of claim 12 , wherein the respective subsequent desired data states of the group of memory cells are the respective final desired data states of the group of memory cells for a programming operation on the array of memory cells.

16. The apparatus of claim 12 , wherein the apparatus is a solid state drive, and the array of memory cells is contained in a memory device of the solid state drive.