Apparatuses and methods for selective determination of data error repair
View Patent ↗Apparatuses and methods are described for selective determination of data error repair. An example apparatus includes a memory array and a controller coupled to the memory array. The controller is configured to direct performance, responsive to a request, of a read operation at an address in the memory array, direct detection of an error in data corresponding to the read operation address, and direct storage of the read operation address in an address error register. The controller is further configured to direct a response be sent to the enable selective determination of data error repair, where the response does not include the read operation address.
1. An apparatus, comprising:
a controller configured to:
direct detection of an error in data in a memory array corresponding to a read operation address in a read operation request;
direct storage of the read operation address in an address error register; and
direct a response to the request be sent to enable selective determination of error repair, wherein the response does not include the read operation address.
2. The apparatus of claim 1 , wherein the controller is further configured, responsive to a host-initiated read of the address error register, to direct initiation of the data error repair.
3. The apparatus of claim 1 , wherein the controller is further configured to direct that a first address error register entry be stored in the address error register until initiation of the data error repair.
4. The apparatus of claim 1 , wherein the request is included in a request packet and the response is included in a response packet that each include a tag to correlate the request packet and the response packet.
5. The apparatus of claim 1 , wherein the controller is further configured to receive the request from a host.
6. The apparatus of claim 1 , wherein the controller is further configured to send the response to a host.
7. The apparatus of claim 1 , wherein the controller is located on a logic base of a hybrid memory cube (HMC).
8. The apparatus of claim 1 , wherein the apparatus comprises a stack of dynamic random access memory (DRAM) dies.
9. An apparatus, comprising:
a memory array; and
a logic base coupled to the memory array and comprising an address error register; and
wherein the logic base is configured to:
perform an error detection operation on data in the memory array corresponding to a read operation address in a read operation request;
responsive to detecting an error in the data, store the read operation address in the address error register; and
enable retrieval of the read operation address from the address error register to selectively determine whether to initiate an error repair operation from a plurality of error repair options.
10. The apparatus of claim 9 , wherein apparatus is configured to:
store read operation addresses of a plurality of detected data errors, corresponding to performance of a number of read operations, in a corresponding plurality of address error registers of the logic base; and
retrieve the read operation addresses of the plurality of detected data errors from the corresponding plurality of address error registers to enable selective determination of whether an error repair operation is initiated for each detected data error.
11. The apparatus of claim 9 , wherein the logic base is further configured to:
contribute to a response sent to a host, wherein the response comprises a notification that the data error is detected; and
contribute to the read operation address of the detected data error being sent to the host responsive to a host-determined retrieval policy.
12. The apparatus of claim 9 , wherein a host-determined retrieval policy is that the response is sent to the host as notification when each data error is detected in the data.
13. The apparatus of claim 9 , wherein a host-determined retrieval policy is that a plurality of responses is sent to the host as notification when a plurality of data errors detected in the data reaches a threshold.
14. An apparatus, comprising:
a host;
a controller coupled to the host via a bus and configured to:
receive a read request that comprises an address for performance of a read operation;
direct that a response to the request be sent to the host, wherein the response includes an indication of a type of data error for an error detected in data corresponding to the read operation address, and wherein the response does not include the read operation address; and
wherein the host is configured to:
retrieve the read operation address; and
selectively determine whether to initiate an error repair operation from a plurality of error repair options.
15. The apparatus of claim 14 , wherein each read operation address:
is stored in an address error register; and
is retrievable from the address error register to the host based on the type of data error.
16. The apparatus of claim 14 , wherein the host is further configured to command that the data error be repaired.
17. The apparatus of claim 14 , wherein the host is further configured to command that the data error not be repaired.
18. The apparatus of claim 14 , wherein:
the controller is one of a plurality of vault controls in a logic base;
the respective plurality of vault controls is selectably coupled to respective memory arrays in a vault of a hybrid memory cube (HMC); and
the respective plurality of vault controls is selectably coupled to the host.
19. The apparatus of claim 14 , wherein the host is configured to selectively determine, based upon a stored repair protocol, whether to initiate the error repair operation from the plurality of error repair options.
20. The apparatus of claim 14 , wherein the type of data error is selected from a group of error types comprising: a single-bit correctable error, a multi-bit correctable error, and a multi-bit uncorrectable error.