Apparatuses and methods for performing logical operations using sensing circuitry
View Patent ↗The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
1. A system, comprising:
a host; and
a memory device coupled to the host and comprising an array coupled to sensing circuitry;
wherein the sensing circuitry comprises a first latch coupled to a sense line of the array, and a second latch coupled to the first latch; and
wherein, responsive to an instruction received from the host, the sensing circuitry is controlled to perform a logical OR operation by:
performing a first operation phase that comprises sensing a memory cell coupled to the sense line; and
performing a number of intermediate operation phases, wherein each one of the number of intermediate operations comprises sensing one of a respective number of different memory cells coupled to the sense line;
wherein subsequent to the number of intermediate operation phases, an accumulated result of the logical OR operation resides in the second latch.
2. The system of claim 1 , wherein the first latch is a latch of a sense amplifier and the second latch is a latch of a compute component.
3. The system of claim 1 , wherein the sensing circuitry is further controlled to obtain a NOR logical operation result by inverting, via an invert signal provided to the compute component, the accumulated result of the logical OR operation residing in the second latch.
4. The system of claim 3 , wherein the sensing circuitry is further controlled to transfer the NOR logical operation result from the second latch to the first latch.
5. The system of claim 3 , wherein the sensing circuitry is controlled to transfer the NOR logical operation result from the second latch to the first latch via enabling of the first latch while the invert signal is provided to the compute component.
6. The system of claim 1 , wherein the host comprises a processor external to the memory device.
7. A system, comprising:
a host; and
a memory device coupled to the host and comprising a controller configured to control sensing circuitry coupled to an array to:
sense, via a sense amplifier coupled to a sense line of the array, a data value serving as a first input of a logical AND operation;
provide the sensed data value to a latch of a compute component coupled to the sense amplifier; and
determine a number of additional data values stored in a number of memory cells coupled to the sense line and serving as a respective number of additional inputs of the logical AND operation; and
wherein a determined result of the logical AND operation is stored in the latch of the compute component.
8. The system of claim 7 , wherein the number of additional data values are determined via respective sense operations via the sense amplifier.
9. The system of claim 7 , wherein the compute component comprises:
a first and a second pair of cross coupled transistors;
a pair of pass transistors; and
a pair of invert transistors.
10. The system of claim 7 , wherein the controller is further configured to control
the sensing circuitry to obtain a NAND logical operation result by inverting, via an invert signal provided to the compute component, the determined result of the logical AND operation stored in the latch of the compute component.
11. A method of operating a system, the method comprising:
receiving instructions at a memory device from a host; and
executing the instructions on the memory device, wherein executing the instructions comprises performing a logical OR operation by:
activating a first access line to which a first memory cell is coupled, the first memory cell storing a data value corresponding to a first input of the logical OR operation;
latching the data value corresponding to the first input in a first latch of sensing circuitry corresponding to a sense line to which the first memory cell is coupled; and
copying, to a second latch of the sensing circuitry, the data value corresponding to the first input;
activating a second access line to which a second memory cell is coupled, the second memory cell storing a data value corresponding to a second input of the logical OR operation;
while the second access line is activated, activating the first latch;
wherein subsequent to activating the first latch while the second access line is activated, the second latch stores an accumulated result of the logical OR operation.
12. The method of claim 11 , wherein the method includes maintaining the second latch in an activated state while the first latch is activated during activation of the second access line.
13. The method of claim 11 , wherein the method includes transferring the accumulated result of the logical OR operation to at least one of: a memory cell of an array comprising the first access line and the second access line; and the first latch.
14. The method of claim 11 , wherein the method further includes obtaining a NOR logical operation result by inverting, via an invert signal provided to a compute component comprising the second latch, the accumulated result of the logical OR operation residing in the second latch.
15. The method of claim 11 , wherein the host is an external host comprising a processor, and wherein the method includes receiving the instructions at the memory device from the processor.
16. A method of operating a system, the method comprising:
receiving instructions at a memory device from a host; and
executing the instructions on the memory device, wherein executing the instructions comprises performing a logical AND operation by:
performing a first operation phase that includes:
activating a first access line of the array, the first access line coupled to a first memory cell storing a data value corresponding to a first input of the logical AND operation;
activating a first latch of sensing circuitry coupled to a sense line to which the first memory cell is coupled in order to latch the data value therein;
activating a second latch of the sensing circuitry to copy the data value latched in the first latch to the second latch; and
performing a second operation phase that includes:
activating a second access line to which a second memory cell is coupled, the second memory cell storing a data value corresponding to a second input of the logical AND operation;
while the second access line is activated, activating the first latch; and
wherein subsequent to activating the first latch while the second access line is activated, the second latch stores an accumulated result of the logical AND operation.
17. The method of claim 16 , wherein the method includes obtaining a NAND logical operation result by inverting, via an invert signal provided to a compute component comprising the second latch, the accumulated result of the logical AND operation stored in the second latch subsequent to the second operation phase.
18. The method of claim 16 , wherein the memory device comprises a controller, and wherein receiving instructions at the memory device comprises receiving instructions to the controller via a host interface.
19. The method of claim 16 , wherein performing the logical AND operation further comprises performing a last operation phase comprising:
copying the accumulated result of the logical AND operation stored in the second latch to a particular memory cell of the array by activating the particular row.
20. The method of claim 16 , wherein the method includes providing the accumulated result of the logical AND operation to the host.