IP Library Granted Patent US 10,504,562
Granted Patent B2
US 10,504,562 · App. 15/919,020 · Granted Dec 10, 2019

Power management integrated circuit load switch driver with dynamic biasing

Inventor: Matthew David Rowley (Boise, ID)
Assignee: MICRON TECHNOLOGY, INC.
G11C5/147G06F1/28G06F1/305G11C5/145H03K17/687
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Quick Facts
Patent No.
US 10,504,562
App. No.
15/919,020
Granted
Dec 10, 2019
Kind
B2
Abstract

Disclosed is an improved load switch driver for power management integrated circuit (PMIC) devices. In one embodiment, a PMIC is disclosed comprising a gate driver, the gate driver connected to the gate of a switch; an operation frequency generator connected to the gate driver and configured to supply a periodic voltage to the gate driver; and a voltage sensor, the voltage sensor connected to the operation frequency generator and the source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch and lower the frequency of the operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage.

Claims (33)

1. A power management integrated circuit (PMIC) comprising:

a gate driver, the gate driver coupled to a gate of a switch;

an operation frequency generator coupled to the gate driver and configured to supply a periodic voltage to the gate driver; and

a voltage sensor, the voltage sensor coupled to the operation frequency generator and a source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch and lower a frequency of the operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage.

2. The PMIC of claim 1 , the gate driver comprising a charge pump.

3. The PMIC of claim 1 , the gate driver comprising a push-pull driver.

4. The PMIC of claim 1 , the switch comprising a MOSFET switch.

5. The PMIC of claim 1 , the periodic voltage supplied at a frequency between 200 and 400 kHz.

6. The PMIC of claim 1 , the second frequency comprising a frequency between 8.5 and 12 kHz.

7. The PMIC of claim 1 , further comprising at least one voltage regulator and at least one sequencer.

8. A system comprising:

an interface;

a power management integrated circuit (PMIC), the PMIC powered by voltages supplied over the interface and including a load switch driver; and

one or more memory devices coupled to the load switch driver of the PMIC via at least one switch, the load switch driver configured to monitor a drain-source voltage of the switch and lower a frequency of an operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage.

9. The system of claim 8 , the interface comprising a SATA or PCI-E interface.

10. The system of claim 8 , the PMIC comprising a second and third load switch driver.

11. The system of claim 10 , the second load switch driver coupled, via a second switch to a DRAM device.

12. The system of claim 11 , the third load switch driver coupled, via a third switch to an ASIC device.

13. The system of claim 8 , the load switch driver comprising:

a gate driver, the gate driver connected to the gate of the switch;

an operation frequency generator connected to the gate driver and configured to supply a periodic voltage to the gate driver; and

a voltage sensor, the voltage sensor connected to the operation frequency generator and a source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch.

14. The system of claim 13 , the gate driver comprising a charge pump.

15. The system of claim 13 , the gate driver comprising a push-pull driver.

16. The system of claim 13 , the switch comprising a MOSFET switch.

17. The system of claim 13 , the periodic voltage supplied at a frequency between 200 and 400 kHz.

18. The system of claim 13 , the second frequency comprising a frequency between 8.5 and 12 kHz.

19. A method comprising:

supplying a gate voltage to a gate of a switch at a first frequency;

monitoring a drain-source voltage of the switch;

determining that the drain-source voltage of the switch has collapsed; and

supplying the gate voltage to the gate of the switch at a second frequency in response to determining that the drain-source voltage has collapsed.

20. The method of claim 1 , wherein the periodic voltage is supplied at the frequency between 200 and 400 kHz and the second frequency comprising a frequency between 8.5 and 12 kHz.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0965 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2018
From: ROWLEY, MATTHEW DAVID
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047057/0366 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 8 TO PATENT SECURITY AGREEMENT Recorded May 7, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 046084/0955 →