Non-volatile memory module architecture to support memory error correction
Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.
1. An apparatus, comprising:
a dynamic random access memory (DRAM);
a non-volatile memory (NVM) coupled to the DRAM;
a register that provides functionality to identify chip failure of the NVM associated with restoring data from the NVM to the DRAM following a loss of system power to the apparatus;
a backup power source configured to provide power to the apparatus during a loss of system power to the apparatus to allow data transfer from the DRAM to the NVM; and
a controller configured to:
receive, from a host device, a first command that is based at least in part on a loss of system power to the apparatus;
transfer data from the DRAM to the NVM based at least in part on receiving the first command from the host device;
receive, from the host device, a second command that s based at east in part on the system power to the apparatus being re-established;
restore the data from the NVM to the DRAM upon receiving the second command from the host device;
identify chip failure of the NVM in the register, the chip failure based at least in part on restoring the data from the NVM to the DRAM; and
operate the apparatus based at least in part on the chip failure identified and according to instructions from a host device.
2. The apparatus of claim 1 , wherein controller is configured to:
adjust a bit of the register to indicate that the chip failure comprises an error in media of the NVM.
3. The apparatus of claim 1 , wherein the controller is configured to:
adjust a bit of the register to indicate that the chip failure comprises an error in the controller.
4. The apparatus of claim 1 , wherein the controller is configured to:
manage error correcting code (ECC) data on the apparatus;
transfer ECC data to and restore ECC data from the non-volatile memory; and
operate the apparatus based at least in part on the ECC data.
5. The apparatus of claim 1 , wherein the backup power source comprises a capacitor.
6. The apparatus of claim 1 , wherein the backup power source comprises a battery.
7. The apparatus of claim 1 , wherein the NVM comprises NAND flash.
8. The apparatus of claim 1 , wherein the DRAM comprises DDR4 DRAM.
9. A method, comprising:
transferring data from a dynamic random access memory (DRAM) of a non-volatile dual inline memory module (NVDIMM) to a non-volatile memory (NVM) of the NVDIMM upon a power loss, wherein the data is routed from the DRAM to the NVM based at least in part on a configuration of the NVDIMM;
restoring the data from the NVM to DRAM upon power to the NVDIMM being re-established;
identifying a chip failure of the NVM in a register of the NVDIMM, the chip failure associated with restoring the data from the NVM memory to the DRAM; and
operating the NVDIMM based at least in part on the chip failure identified and according to instructions from a host device.
10. The method of claim 9 , further comprising:
determining that the chip failure comprises an error in media of the NVM, wherein one of the bits written in the register is indicative of the error in the non-NVM media.
11. The method of claim 9 , further comprising:
determining that the chip failure comprises an error in a controller associated with the NV wherein one of the bits written in the register is indicative of the error in the controller.
12. The method of claim 9 , further comprising:
storing error correcting code (ECC) data on the DRAM, wherein the data transferred to the NVM and restored to the DRAM comprises the ECC data; and
operating the NVDIMM based at least in part on the ECC data.
13. The method of claim 9 , further comprising:
receiving a first command from the host device that is based at least in part on the system power loss, wherein the data is transferred upon receiving the command; and
receiving a second command from the host device that is based at least in part on the power to the NVDIMM being re-established, wherein the data is restored to the DRAM and the register is written following the second command.
14. The method of claim 9 , wherein the data comprises corrupted data transferred from and restored to the DRAM.