Configurable operating mode memory device and methods of operation

1. A memory device, comprising:

an array of memory cells comprising a plurality of access lines, wherein each access line of the plurality of access lines is configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, and wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines; and

a controller having a plurality of selectively-enabled operating modes;

wherein the controller is configured to operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells;

wherein one operating mode of the plurality of selectively-enabled operating modes is configured to provide access to data of the memory device for providing output of that accessed data from the memory device;

wherein a different operating mode of the plurality of selectively-enabled operating modes is configured to provide access to data of the memory device for providing output of information from the memory device that is different from that accessed data and is responsive to that accessed data; and

wherein the different operating mode of the plurality of selectively-enabled operating modes is configured to provide access to data of the memory device for providing output indicating whether a match occurred between an input data pattern and that accessed data.

2. The memory device of claim 1 , wherein the output indicating whether a match occurred is selected from a group consisting of an indication that a complete match occurred, an indication that a partial match occurred, and an address of that accessed data where the match occurred.

3. A memory device, comprising:

an array of memory cells comprising a plurality of access lines, wherein each access line of the plurality of access lines is configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, and wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines; and

a controller having a plurality of selectively-enabled operating modes selected from a group consisting of a user data storage operating mode, a programmable logic device operating mode, a content addressable memory operating mode, and a neural network operating mode;

wherein the controller is configured to selectively operate the memory device using one or more enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells.

4. The memory device of claim 3 , wherein the controller is further configured to selectively operate the memory device using different operating modes at different times.

5. The memory device of claim 3 , wherein the controller is further configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

6. The memory device of claim 5 , wherein the controller is further configured to selectively alter the assigned respective portions of the array of memory cells for any enabled operating mode of the two or more enabled operating modes.

7. A method of operating a memory device, comprising:

enabling a first operating mode of a plurality of selectively-enabled operating modes of the memory device for access of a first portion of an array of memory cells of the memory device, wherein the array of memory cells comprises a plurality of access lines, wherein each access line of the plurality of access lines is configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, and wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines; and

enabling a second operating mode of the plurality of selectively-enabled operating modes for access of a second portion of the array of memory cells, wherein the second operating mode is different from the first operating mode, and wherein the second portion is different from the first portion; and

concurrently operating the memory device utilizing the first operating mode and the second operating mode;

wherein the plurality of selectively-enabled operating modes are selected from a group consisting of a user data storage operating mode, a programmable logic device operating mode, a content addressable memory operating mode, and a neural network operating mode.