IP Library Granted Patent US 10,297,611
Granted Patent B1
US 10,297,611 · App. 15/903,307 · Granted May 21, 2019

Transistors and arrays of elevationally-extending strings of memory cells

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Quick Facts
Patent No.
US 10,297,611
App. No.
15/903,307
Granted
May 21, 2019
Kind
B1
Abstract

A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

Claims (49)

1. An array of elevationally-extending strings of memory cells, comprising:

a vertical stack of alternating insulative tiers and wordline tiers, the wordline tiers having terminal ends corresponding to control-gate regions of individual memory cells;

a charge-blocking region of the individual memory cells extending elevationally along the individual control-gate regions;

charge-storage material of the individual memory cells extending elevationally along individual of the charge-blocking regions;

channel material extending elevationally along the stack, the channel material having a laterally-inner side;

insulative charge-passage material laterally between the channel material and the charge-storage material;

a first insulating material having first and second opposing sides, the first side being adjacent the laterally-inner side of the channel material, the first insulating material comprising a tube; and

a second insulating material of different composition from that of the first insulating material and adjacent the second side of the first insulating material, the second insulating material comprising a tube radially inside of the first-insulating-material tube, the second insulating material having at least one of (a), (b), and (c), where,

(a): lower oxygen diffusivity than the first material;

(b): net positive charge;

(c): at least two times greater shear strength than the first material.

2. The array of claim 1 wherein the first insulating material is directly against the laterally-inner side of the channel material.

3. The array of claim 1 wherein the second insulating material is directly against the second side of the first insulating material.

4. The array of claim 1 comprising a radially-central dielectric material radially inside of the second-insulating-material tube.

5. The array of claim 4 wherein the radially-central dielectric material comprises solid dielectric material.

6. The array of claim 5 wherein the solid dielectric material is a solid pillar.

7. The array of claim 5 wherein the radially-central dielectric material comprises void space.

8. The array of claim 4 wherein the radially-central dielectric material is devoid of solid material.

9. An array of elevationally-extending strings of memory cells, comprising:

a vertical stack of alternating insulative tiers and wordline tiers, the wordline tiers having terminal ends corresponding to control-gate regions of individual memory cells;

a charge-blocking region of the individual memory cells extending elevationally along the individual control-gate regions;

charge-storage material of the individual memory cells extending elevationally along individual of the charge-blocking regions;

channel material extending elevationally along the stack, the channel material having a laterally-inner side;

insulative charge-passage material laterally between the channel material and the charge-storage material;

a first insulating material having first and second opposing sides, the first side being adjacent the laterally-inner side of the channel material, the first insulating material comprising at least one of Si x O y (x and y each greater than 0), Si x O y N z (x, y, and z each greater than 0), Al 3 O 4 , ZrO 2 , HfO 2 , Pr 2 O 3 , and Ta 2 O 5 ; and

a second insulating material of different composition from that of the first insulating material and adjacent the second side of the first insulating material, the second insulating material comprising at least one of Al 2 O 3 , HfN, HfO x N y (x and y each greater than 0), HfY x O y (x and y each greater than 0), BN, AlN, SiC, diamond, diamond-like carbon, Si x N y H z (x, y, and z each greater than 0), Hf x N y H z (x, y, and z each greater than 0), HfO x N y H z (x, y, and z each greater than 0), HfY x O y H z (x, y, and z each greater than 0), BN x H y (x and y each greater than 0), and AlN x H y (x and y each greater than 0).

10. The array of claim 9 wherein the first side of the first insulating material is directly against the laterally-inner side of the channel material and the at least one of Si x O y , Si x O y N z , Al 3 O 4 , ZrO 2 , HfO 2 , Pr 2 O 3 , and Ta 2 O 5 is directly against the laterally-inner side of the channel material.

11. The array of claim 9 wherein the second insulating material is directly against the second side of the first insulating material and the at least one of Al 2 O 3 , HfN, HfO x N y , HfY x O y , BN, AlN, SiC, diamond, diamond-like carbon, Si x N y H z , Hf x N y H z , HfO x N y H z , HfY x O y H z , BN x H y , and AlN x H y is directly against the at least one of Si x O y , Si x O y N z , Al 3 O 4 , ZrO 2 , HfO 2 , Pr 2 O 3 , and Ta 2 O 5 of the first insulating material.

12. The array of claim 9 wherein the first insulating material comprises a tube and the second insulating material comprises a tube radially inside of the first-insulating-material tube.

13. The array of claim 12 comprising a radially-central dielectric material radially inside of the second-insulating-material tube.

14. The array of claim 13 wherein the radially-central dielectric material comprises solid dielectric material.

15. The array of claim 14 wherein the solid dielectric material is a solid pillar.

16. The array of claim 13 wherein the radially-central dielectric material comprises void space.

17. The array of claim 9 wherein the radially-central dielectric material is devoid of solid material.

18. The array of claim 9 wherein the second insulating material comprises Al 2 O 3 .

19. The array of claim 9 wherein the second insulating material comprises HfN.

20. The array of claim 9 wherein the second insulating material comprises HfO x N y .

21. The array of claim 9 wherein the second insulating material comprises HfY x O y .

22. The array of claim 9 wherein the second insulating material comprises BN.

23. The array of claim 9 wherein the second insulating material comprises AlN.

24. The array of claim 9 wherein the second insulating material comprises, SiC.

25. The array of claim 9 wherein the second insulating material comprises diamond.

26. The array of claim 9 wherein the second insulating material comprises diamond-like carbon.

27. The array of claim 9 wherein the second insulating material comprises Si x N y H z .

28. The array of claim 9 wherein the second insulating material comprises Hf x N y H z .

29. The array of claim 9 wherein the second insulating material comprises HfO x N y H z .

30. The array of claim 9 wherein the second insulating material comprises HfY x O y H z .

31. The array of claim 9 wherein the second insulating material comprises BN x H y .

32. The array of claim 9 wherein the second insulating material comprises AlN x H y .

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0965 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 8 TO PATENT SECURITY AGREEMENT Recorded May 7, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 046084/0955 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2018
From: WELLS, DAVID H.; TRAN, LUAN C.; LI, JIE; KHANDEKAR, ANISH A.; SHROTRI, KUNAL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045016/0536 →