Apparatuses and methods for refresh control
Apparatuses and methods of for refresh control of a semiconductor device are described. An example apparatus includes a command control circuit that provides a plurality of pulses on a first control signal in series responsive to a plurality of refresh commands issued in series; a signal generation circuit that produces a plurality of pulses on a second control signal in sequence; and a refresh control circuit that receives two or more of the plurality of pulses on the first control signal during a period of time between one pulse and a succeeding pulse of the plurality of pulses on the second control signal, disables refresh operations responsive to at least one of the two or more of the plurality of first control signal and executes a refresh operation responsive to remaining one or more pulses of the two or more of the plurality of pulses on the first control signal.
1. An apparatus comprising:
a refresh control circuit configured to receive a first control signal and a second control signal,
wherein the refresh control circuit comprises:
a first circuit configured to provide a first signal responsive to the first control signal and a latch signal, the latch signal responsive to the second control signal; and
a multiplexer configured to provide a third signal responsive to either the first signal or a second signal, the second signal provided to the multiplexer responsive to the second control signal and the latch signal, and
wherein the refresh control circuit is further configured to:
receive two or more of a plurality of pulses in the first control signal during a period of time between one pulse and a succeeding pulse of a plurality of pulses on the second control signal,
disable refresh operations in response to one of the two or more of a plurality of pulses on the first control signal, and
execute a refresh operation in response to a remaining one or more pulses of the two or more of the plurality of pulses on the first control signal in a normal operation mode.
2. The apparatus of claim 1 , wherein the first control signal is an auto-refresh (AREF) command signal and the second control signal is an oscillator (OSC) signal.
3. The apparatus of claim 1 , further comprising:
a signal generation circuit configured to generate, in a self-refresh operation mode, an internal refresh signal responsive to the second control signal.
4. The apparatus of claim 1 , wherein the refresh control circuit further comprises a latch circuit configured to provide the latch signal responsive to the second control signal; and
wherein the multiplexer is configured to provide, as the third signal, the first signal in the normal operation mode, and the second signal in a self-refresh operation mode.
5. The apparatus of claim 1 , wherein the refresh control circuit further comprises:
a latch circuit configured to provide the latch signal responsive to the second control signal; and
a second circuit configured to provide the second signal responsive to the second control signal and the latch signal, and
wherein the multiplexer is configured to provide, as the third signal, the first signal in the normal operation mode, and the second signal in a self-refresh operation mode.
6. The apparatus of claim 1 , wherein the refresh control circuit further comprises:
a one shot pulse generator configured to provide a one shot pulse signal responsive to the third signal,
a latch circuit configured to provide the latch signal responsive to the second control signal received by a set input of the latch circuit; and
a second circuit configured to provide the second signal responsive to the second control signal and the latch signal.
7. The apparatus of claim 6 , wherein, in the normal operation mode, the multiplexer is configured to provide, as the third signal, the first signal provided by the first circuit, and
wherein, in a self-refresh operation mode, the multiplexer is configured to provide, as the third signal, the second signal provided by the second circuit.