Apparatus and methods of operating memory for negative gate to body conditions

1. A method of operating a memory, comprising:

applying a first voltage level to a first voltage node electrically connected to a first end of a string of series-connected memory cells;

applying a second voltage level to a second voltage node electrically connected to a second end of the string of series-connected memory cells;

applying a third voltage level to a control gate of a first memory cell of the string of series-connected memory cells while applying the first voltage level to the first voltage node and while applying the second voltage level to the second voltage node, wherein the third voltage level is less than the first voltage level and less than the second voltage level; and

applying a fourth voltage level to a control gate of a second memory cell of the string of series-connected memory cells while applying the third voltage level to the control gate of the first memory cell, wherein the fourth voltage level is less than the third voltage level, and wherein the first memory cell is closer to the first voltage node than the second memory cell.

2. The method of claim 1 , wherein the string of series-connected memory cells comprises a plurality of diode drops, wherein applying the third voltage level to the control gate of the first memory cell comprises applying the third voltage level to a control gate of a memory cell of the string of series-connected memory cells that is electrically connected to the first voltage node without any intervening diode drops of the plurality of diode drops, and wherein applying the fourth voltage level to the control gate of the second memory cell comprises applying the fourth voltage level to a control gate of a memory cell of the string of series-connected memory cells that is electrically connected to the first voltage node through one diode drop of the plurality of diode drops.

3. The method of claim 1 , further comprising:

applying a fifth voltage level to a control gate of a third memory cell of the string of series-connected memory cells while applying the third voltage level to the control gate of the first memory cell;

wherein the second memory cell is closer to the first voltage node than the third memory cell; and

wherein the fifth voltage level is less than the fourth voltage level.

4. The method of claim 1 , further comprising:

applying a fifth voltage level to a control gate of a third memory cell of the string of series-connected memory cells while applying the third voltage level to the control gate of the first memory cell;

wherein the second memory cell is closer to the first voltage node than the third memory cell; and

wherein the fifth voltage level is greater than or equal to the fourth voltage level.

5. The method of claim 4 , further comprising:

wherein applying the fifth voltage level to the control gate of the third memory cell comprises applying a voltage level equal to the fourth voltage level;

wherein the string of series-connected memory cells comprises a plurality of diode drops;

wherein a particular number of diode drops of the plurality of diode drops are between the second memory cell and the first voltage node;

wherein the particular number of diode drops of the plurality of diode drops are between the third memory cell and the second voltage node; and

wherein the first voltage level and the second voltage level are a same voltage level.

6. The method of claim 4 , further comprising:

wherein applying the fifth voltage level to the control gate of the third memory cell comprises applying a voltage level equal to the third voltage level;

wherein the string of series-connected memory cells comprises a plurality of diode drops;

wherein a particular number of diode drops of the plurality of diode drops are between the first memory cell and the first voltage node;

wherein the particular number of diode drops of the plurality of diode drops are between the third memory cell and the second voltage node; and

wherein the first voltage level and the second voltage level are a same voltage level.

7. The method of claim 4 , further comprising:

wherein applying the fifth voltage level to the control gate of the third memory cell comprises applying a voltage level greater than the third voltage level;

wherein the string of series-connected memory cells comprises a plurality of diode drops;

wherein a particular number of diode drops of the plurality of diode drops are between the first memory cell and the first voltage node;

wherein a number of diode drops of the plurality of diode drops between the third memory cell and the second voltage node is less than the particular number; and

wherein the first voltage level and the second voltage level are a same voltage level.

8. A method of operating a memory, comprising:

applying a first voltage level to a first voltage node electrically connected to a first end of a string of series-connected memory cells, wherein the string of series-connected memory cells is arranged as a plurality of groupings of series-connected memory cells, with each grouping of series-connected memory cells of the plurality of groupings of series-connected memory cells electrically connected to an adjacent grouping of series-connected memory cells of the plurality of groupings of series-connected memory cells through a respective diode drop of a plurality of diode drops;

applying a second voltage level to a second voltage node electrically connected to a second end of the string of series-connected memory cells; and

while applying the first voltage level to the first voltage node and applying the second voltage level to the second voltage node:

applying a third voltage level, less than the first voltage level and less than the second voltage level, to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to a first integer value; and

applying a fourth voltage level, less than the third voltage level, to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to a second integer value that is one greater than the first integer value.

9. The method of claim 8 , further comprising:

applying the third voltage level to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the second voltage node through a number of diode drops of the plurality of diode drops equal to the first integer value; and

applying the fourth voltage level to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the second voltage node through a number of diode drops of the plurality of diode drops equal to the second integer value.

10. The method of claim 9 , wherein applying the fourth voltage level to the respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to the second integer value and applying the fourth voltage level to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the second voltage node through a number of diode drops of the plurality of diode drops equal to the second integer value comprises applying the fourth voltage level to the respective control gate of each memory cell of a single grouping of memory cells of the plurality of groupings of memory cells.

11. The method of claim 8 , further comprising:

applying a fifth voltage level, less than the fourth voltage level, to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to a third integer value that is one greater than the second integer value.

12. The method of claim 11 , further comprising:

applying the third voltage level to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the second voltage node through a number of diode drops of the plurality of diode drops equal to the first integer value;

applying the fourth voltage level to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the second voltage node through a number of diode drops of the plurality of diode drops equal to the second integer value; and

applying the fifth voltage level to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the second voltage node through a number of diode drops of the plurality of diode drops equal to the third integer value.

13. The method of claim 12 , wherein applying the first voltage level to the first voltage node and applying the second voltage level to the second voltage node comprises applying a same voltage level to the first voltage node and to the second voltage node.

14. The method of claim 8 , wherein applying the third voltage level to the respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to the first integer value comprises applying the third voltage level to the respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node through zero diode drops.

15. The method of claim 8 , wherein applying the fourth voltage level to the respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to the second integer value comprises memory cells of the string of series-connected memory cells that are also electrically connected to the second voltage node through a number of diode drops of the plurality of diode drops equal to a third integer value greater than or equal to the second integer value.

16. The method of claim 8 , further comprising:

applying a fifth voltage level, greater than the third voltage level, to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node without any intervening diode drops of the plurality of diode drops.

17. The method of claim 8 , wherein the plurality of diode drops has an integer value N number of diode drops, the method further comprising:

for each integer value for X greater than or equal to zero and less than or equal to N/2, applying a corresponding voltage level to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to X and to a respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the second voltage node through a number of diode drops of the plurality of diode drops equal to X;

wherein the corresponding voltage level for a particular integer value for X is different than the corresponding voltage level for any other integer value for X.

18. The method of claim 17 , wherein a number of memory cells of the string of series-connected memory cells electrically connected to the first voltage node through zero diode drops is greater than or equal to zero, and wherein a number of memory cells of the string of series-connected memory cells electrically connected to the second voltage node through zero diode drops is greater than or equal to zero.

19. The method of claim 18 , wherein the number of memory cells of the string of series-connected memory cells electrically connected to the first voltage node through zero diode drops is greater than the number of memory cells of the string of series-connected memory cells electrically connected to the second voltage node through zero diode drops.

20. The method of claim 8 , wherein applying the third voltage level to the respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to the first integer value and applying the fourth voltage level to the respective control gate of each memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to the second integer value comprises applying the third voltage level and applying the fourth voltage level to a different number of control gates.

21. An apparatus, comprising:

a string of series-connected memory cells;

a first voltage node selectively electrically connected to a first end of the string of series-connected memory cells;

a second voltage node selectively electrically connected to a second end of the string of series-connected memory cells; and

a controller, wherein the controller is configured to:

apply a first voltage level to the first voltage node while electrically connected to the first end of the string of series-connected memory cells;

apply a second voltage level to the second voltage node while electrically connected to the second end of the string of series-connected memory cells;

apply a third voltage level to a control gate of a first memory cell of the string of series-connected memory cells while applying the first voltage level to the first voltage node and while applying the second voltage level to the second voltage node, wherein the third voltage level is less than the first voltage level and less than the second voltage level; and

apply a fourth voltage level to a control gate of a second memory cell of the string of series-connected memory cells while applying the third voltage level to the control gate of the first memory cell, wherein the fourth voltage level is less than the third voltage level, and wherein the first memory cell is closer to the first voltage node than the second memory cell.

22. The apparatus of claim 21 , wherein the string of series-connected memory cells is arranged as a plurality of groupings of series-connected memory cells, with each grouping of series-connected memory cells of the plurality of groupings of series-connected memory cells electrically connected to an adjacent grouping of series-connected memory cells of the plurality of groupings of series-connected memory cells through a respective diode drop of a plurality of diode drops, and wherein the controller is further configured to:

apply the third voltage level to the control gate of the first memory cell and to a respective control gate of each remaining memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to a first integer value; and

apply the fourth voltage level to the control gate of the second memory cell and to a respective control gate of each remaining memory cell of the string of series-connected memory cells electrically connected to the first voltage node through a number of diode drops of the plurality of diode drops equal to a second integer value that is one greater than the first integer value.