IP Library Granted Patent US 10,224,479
Granted Patent B2
US 10,224,479 · App. 15/882,666 · Granted Mar 5, 2019

Phase change memory stack with treated sidewalls

Inventors: Tsz W. Chan (Boise, ID); Yongjun Jeff Hu (Boise, ID); Swapnil Lengade (Boise, ID); Shu Qin (Boise, ID); Everett Allen McTeer (Eagle, ID)
Assignee: Micron Technology, Inc.
H01L45/06G11C13/0004H01L27/2409H01L27/2481H01L45/12H01L45/1233H01L45/1253H01L45/141H01L45/16H01L45/165H01L45/1616H01L45/1675
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Quick Facts
Patent No.
US 10,224,479
App. No.
15/882,666
Granted
Mar 5, 2019
Kind
B2
Abstract

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

Claims (32)

1. A method of fabricating a memory stack, comprising:

forming the memory stack comprising multiple stacked elements, the memory stack defined in part by sidewalls;

forming an adhesion species on at least one sidewall of the memory stack, including intermixing the adhesion species with an element of the memory stack, and further including forming a film of the adhesion species on an outer surface of the intermixed adhesion species; and

implanting a dielectric material into the adhesion species film.

2. The method of claim 1 , wherein intermixing the adhesion species with the element comprises implanting the adhesion species into the sidewall of the element.

3. The method of claim 2 , wherein implanting the adhesion species into the sidewall of the element comprises performing a plasma doping process at an energy less than 3 keV.

4. The method of claim 1 , wherein implanting the dielectric material into the adhesion species film comprises a plasma doping process at an energy within the range of 0-2 keV.

5. The method of claim 1 , wherein forming the adhesion species comprises performing both a plasma doping process and a deposition process.

6. The method of claim 5 , wherein performing the plasma doping process comprises performing a plasma doping of boron into the sidewall of the element of the memory stack.

7. The method of claim 6 , wherein implanting the dielectric material into the film comprises implanting a nitride forming material into the film to form a boron and nitride (BN X ) dielectric film.

8. The method of claim 1 , wherein forming the memory stack comprising forming multiple stacked elements comprising:

forming a word line material;

forming a first electrode material over the word line material;

forming a variable resistance material over the second electrode material; and

forming a second electrode material over the phase change material.

9. The method of claim 8 , wherein at east one of the first and second electrode materials includes carbon.

10. The method of claim 9 , wherein the boron adhesion species terminates unsatisfied atomic bonds of the carbon.

11. The method of claim 8 , wherein forming the word line material comprises forming a material including tungsten.

12. A method for fabricating a memory device comprising:

forming multiple memory stacks defined in part by sidewalls, each memory stack fabricated by:

forming a first electrode over a word line material;

forming a variable resistance material over the first electrode;

forming a second electrode over the variable resistance material; and

patterning and etching the first and second electrodes and the variable resistance material to form the multiple memory stacks;

forming an adhesion species on at least one sidewall of each of multiple memory stacks using a doping process and a deposition process, wherein the adhesion species comprises a first portion implanted to intermix with at least one element of the memory stack, and a second portion comprising a film of the adhesion species over the first portion; and

forming a liner material on the sidewalls of multiple memory stacks by implanting a dielectric material into the film of the adhesion species.

13. The method of claim 12 , wherein forming the adhesion species comprises forming a gradient structured adhesion species on the sidewalls, comprising:

using a plasma doping process to implant a boron species; and

using a deposition process to form a boron film on the sidewall over the implanted boron species.

14. The method of claim 12 , wherein forming the liner material comprises forming a boron and nitride (BN X ) liner material over at least one of the first and second electrodes.

15. The method of claim 12 , further comprising forming a dielectric fill material between pairs of the memory stacks.

16. The method of claim 12 , wherein forming the liner material comprises forming the liner material through a plasma doping process at a temperature of less than 390□ C.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0965 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 8 TO PATENT SECURITY AGREEMENT Recorded May 7, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 046084/0955 →
Continuity (3)
Continuation 15090292 · Apr 4, 2016
Division 14266415 · Apr 30, 2014
Related Publication 20180166629A1 · Jun 14, 2018