Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers

1. A method, comprising:

accessing data in a first region of memory cells of a memory system, wherein the memory cells of the memory system are divided into channels, each channel comprising multiple memory cells, and wherein the data is accessed in accordance with a first address definition including one or more bits identifying a first channel depth to be accessed, wherein the channel depth is a number of bytes accessed in the channel before going to another channel; and

accessing data in a second region of memory cells of the memory system, wherein the data in the second region is accessed in accordance with a second address definition including one or more bits identifying a second channel depth to be accessed, wherein the first and second channel depths are different from one another; and

wherein the channel depth bits are located in a different positions in the second address definition than in the first address definition.

2. The method of claim 1 , wherein accessing data in the second region of memory cells further comprises accessing the data in the second region of memory cells with less power than is used to access data in the first region of memory cells.

3. The method of claim 2 , wherein the channel depth in the second region of memory cells is deeper than the channel depth in the first region of memory cells.

4. The method of claim 3 , wherein the channel depth bits of the first address definition are of a lower order than the channel depth bits of the second address definition.

5. The method of claim 1 , wherein the first and second address definitions each include multiple bits defining a respective row address and column address in addition to the channel depth.

6. The method of claim 5 , wherein each of the first and second address definitions further includes a respective region address.

7. The method of claim 1 , wherein accessing data in the second region of memory cells further comprises accessing the data in the first region of memory cells with a greater latency than is used to access data in the second region of memory cells.

8. The method of claim 7 , wherein the channel depth in the first region of memory cells is shallower than the channel depth in the second region of memory cells.

9. A method comprising:

receiving first and second data at a memory system in respective first and second memory commands from respective first and second masters;

writing the first data to the first region of memory cells of a memory system through use of a first address definition when the master is of a first type, the first region having a first channel depth, and the address definition including one or more channel depth bits in a first position in the first address definition; and

writing the second data to the second region of memory cells of the memory system through use of a second address definition when the master is of a second type, the second region having a second channel depth different from the first channel depth, wherein the first address definition is different than the second address definition.

10. The method of claim 9 , wherein the first data is written to the first region when the first master is more tolerant of latency than the second master.

11. The method of claim 9 , wherein:

the first data is written to the first region when the first master comprises a general processor; and

the second data is written to the second region when the second master comprises a graphics processor.

12. The method of claim 11 , wherein the second channel depth of the second region is deeper than the first channel depth.