Resistance variable element methods and apparatuses

1. A method, comprising:

performing a program operation on a first resistance variable element coupled to a first access device, the first resistance variable element and the first access device being coupled between a first data line and a common source, wherein performing the program operation comprises,

providing the first access device with a first control gate voltage at a first time interval of a programming operation, and with a second control gate voltage at a second time interval of a programming operation, wherein the second control gate voltage is greater than the first control gate voltage,

establishing the common source at a source voltage that is substantially the same during each of the first and second time intervals; and

performing one of the two following operations,

establishing a first data line voltage on the first data line during the first time interval to write a first program state to the first resistance variable element, wherein the first data line voltage is less than the common source voltage, and

establishing a second data line voltage on the first data line during the second time interval to write a second program state to the first resistance variable element, wherein the second data line voltage is greater than the common source voltage.

2. The method of claim 1 , wherein the first access device comprises a first field-effect transistor having a gate, and wherein each of the first and second control gate voltages are applied to the gate of the first field-effect transistor.

3. The method of claim 1 , wherein the first control gate voltage established during the first time interval increases directly to establish the second control gate voltage during the second time interval before decreasing to a rest voltage, thereby forming a single pulse with different levels during the first and second time intervals.

4. The method of claim 1 , wherein the first control gate voltage is applied during a first pulse, and the second control gate voltage is applied during a second pulse.

5. The method of claim 1 , further comprising providing a common source voltage of approximately 1.5 volts to the common source during the first and second time intervals.

6. The method of claim 1 , wherein the second control gate voltage is substantially equal to the first control gate voltage plus the common source voltage.

7. The method of claim 3 , wherein the common source voltage is maintained substantially constant during the first and second time intervals.

8. The method of claim 1 , wherein the first resistance variable element is located in series between the common source and the first access device.

9. The method of claim 1 , wherein the access device is located in series between the common source and the resistance variable element.

10. A method of operating an array of resistance variable memory cells, comprising:

providing a common source voltage to a common source coupled to multiple memory cells in the array, wherein the resistance variable memory cells each comprise,

a variable resistance element, and

an access device having a control gate, and

wherein the access device and resistance variable element are coupled in series between the common source and a respective data line;

providing multiple data lines with a standby data line voltage, wherein each data line is coupled to a respective group of memory cells of the multiple memory cells;

providing the control gates of multiple access devices with a first control gate voltage during a first time interval, and with a second control gate voltage during a second time interval, wherein the second control gate voltage is greater than the first control gate voltage;

providing a first data line voltage to a first data line during the first time interval to program a first resistance variable element in a first memory cell connected to the first data line to a first program state; and

providing a second data line voltage to a second data line during the second time interval to program a second resistance variable element in a second memory cell connected to the second data line to a second program state.

11. The method of claim 10 , wherein the standby data line voltage is substantially equal to the common source voltage.

12. The method of claim 10 , wherein the first data line voltage is less than the standby data line voltage.

13. The method of claim 12 , wherein the first data line voltage is less than both the standby data line voltage and the common source voltage.

14. The method of claim 10 , wherein the second data line voltage is greater than the standby data line voltage.

15. The method of claim 14 , wherein the second data line voltage is greater than both the standby data line voltage and the common source voltage.

16. The method of claim 10 , wherein:

providing multiple access devices with the first control gate voltage comprises raising a gate terminal of the multiple access devices from a reference voltage to the first control gate voltage; and

providing the multiple access devices with the second control gate voltage comprises raising a gate terminal of the multiple access devices from the reference voltage to the second control gate voltage.

17. The method of claim 10 , wherein:

providing multiple access devices with the first control gate voltage comprises raising a gate terminal of the multiple access devices from a reference voltage to the first control gate voltage; and

providing the multiple access devices with the second control gate voltage comprises raising a gate terminal of the multiple access devices from the first control gate voltage to the second control gate voltage.

18. The method of claim 10 , wherein the standby data line voltage is equal with the common source voltage.

19. An resistance variable memory cell assembly, comprising:

a common source coupled to an array of resistance variable memory cells;

multiple data lines, each data line coupled to a respective group of resistance variable memory cells of the array;

wherein the multiple resistance variable memory cells each include a resistance variable element and an access device having a gate terminal, the access device and the resistance variable element coupled in series between the common source and a respective data line;

a memory control unit configured to control:

provision of a common source voltage to a common source coupled to multiple memory cells in the array,

provision of a standby data line voltage to multiple data lines,

provision of a first control gate voltage to the control gates of multiple access devices during a first time interval of programming operations, and provision of a second control gate voltage to the control gates of the multiple access devices during a second time interval of the programming operations, wherein the second control gate voltage is greater than the first control gate voltage;

provision of a first data line voltage to a first data line during the first time interval of a first programming operation to program a first resistance variable element in a first memory cell connected to the first data line to a “1”;

provision of a second data line voltage to a second data line during the second time interval of a second programming operation to program a second resistance variable element in a second memory cell connected to the second data line to a “0”.

20. The resistance variable memory cell assembly of claim 19 , wherein provision of the first and second control gate voltages to the multiple access devices comprises,

raising a gate terminal of the multiple access devices from a reference voltage to the first control gate voltage; and

raising a gate terminal of the multiple access devices from the reference voltage to the second control gate voltage.

21. The resistance variable memory cell assembly of claim 19 , wherein provision of the first and second control gate voltages to the multiple access devices comprises,

raising a gate terminal of the multiple access devices from a reference voltage to the first control gate voltage; and

raising a gate terminal of the multiple access devices from the first control gate voltage to the second control gate voltage.

22. The resistance variable memory cell assembly of claim 19 , wherein the first data line voltage is less than both the standby data line voltage and the common source voltage.

23. The resistance variable memory cell assembly of claim 19 , wherein the second data line voltage is greater than both the standby data line voltage and the common source voltage.