Microelectronic package structures including redistribution layers
View Patent ↗A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.
1. A microelectronic package structure, comprising:
a substrate;
first connectors located over the substrate;
redistribution layers located directly over the first connectors, and a first side of the redistribution layers connected to the substrate using the first connectors, each of the redistribution layers comprising:
a block material;
a dielectric material over the block material; and
metal segments located within openings of the dielectric material;
a first passivation material located between the substrate and the first side of the redistribution layers, the first connectors extending through openings in the first passivation material and through openings in the block material of the redistribution layer nearest the substrate;
second connectors located directly over a second side of the redistribution layers opposite the first side of the redistribution layers, the second connectors extending through openings in a second passivation material located on the second side of the redistribution layers, and the second passivation material located directly on the dielectric material of the redistribution layer nearest the second connectors, wherein the dielectric material and the metal segments of the redistribution layer nearest the second connectors are coplanar; and
at least one die connected to the metal segments of the redistribution layer nearest the second connectors on the second side of the redistribution layers using the second connectors, each of the second connectors comprising a single element in direct contact with the at least one die and the metal segments of the redistribution layer nearest the second connectors, wherein the at least one die is electrically connected to the substrate only through the redistribution layers.
2. The microelectronic package structure of claim 1 , wherein the first connectors connect to the metal segments of the redistribution layer nearest the substrate on the first side of the redistribution layers.
3. The microelectronic package structure of claim 1 , wherein the block material comprises silicon carbide, silicon nitride, or a combination thereof.
4. The microelectronic package structure of claim 1 , wherein the metal segments are horizontally aligned, and different layers of the metal segments are connected by vias penetrating the block material therebetween.
5. The microelectronic package structure of claim 1 , wherein the first connectors extend through a bottommost layer of the block material and connect a bottommost layer of the metal segments and the substrate.
6. The microelectronic package structure of claim 1 , wherein the first connectors and the second connectors comprise a solder bump or a solder ball.
7. The microelectronic package structure of claim 1 , wherein each of the first passivation material and the second passivation material comprises silicon oxide, silicon nitride, benzocyclobutene, polyimide, polybenzoxazole, or a combination thereof.
8. A microelectronic device package, comprising:
a substrate;
at least one die electrically connected to the substrate;
redistribution layers providing direct electrical connection between the at least one die and the substrate, the at least one die being electrically connected to the substrate only through the redistribution layers, each of the redistribution layers comprising:
a block material;
a dielectric material located on the block material; and
metal segments located within openings of the dielectric material;
first interconnect structures located between the substrate and the redistribution layers;
second interconnect structures located between the at least one die and the redistribution layers, each of the second interconnect structures comprising a single element in direct contact with the at least one die and the metal segments of the redistribution layer nearest the at least one die;
a first passivation material located between the substrate and the block material of the redistribution layer nearest the substrate, the first interconnect structures extending through openings in the first passivation material and through openings in the block material of the redistribution layer nearest the substrate; and
a second passivation material located between the at least one die and the dielectric material of the redistribution layer nearest the at least one die, the second passivation material located directly on the dielectric material of the redistribution layer nearest the at least one die, and the second interconnect structures extending through openings in the second passivation material, wherein the dielectric material and the metal segments of the redistribution layer nearest the at least one die are coplanar.
9. The microelectronic device package of claim 8 , wherein:
the redistribution layers are in contact with the substrate through the first interconnect structures located between the substrate and the metal segments of the redistribution layer nearest the substrate; and
the redistribution layers are in contact with the at least one die through the second interconnect structures located between the at least one die and the metal segments of a of the redistribution layer nearest the at least one die.
10. The microelectronic device package of claim 8 , wherein:
the first interconnect structures are in direct physical contact with the metal segments of the redistribution layer nearest the substrate; and
the second interconnect structures are in direct physical contact with the metal segments of the redistribution layer nearest the at least one die.
11. The microelectronic device package of claim 8 , further comprising third interconnect structures located on a side of the substrate opposite the first interconnect structures.
12. The microelectronic device package of claim 8 , further comprising vias connecting the metal segments of separate redistribution layers, the vias extending through openings within intervening block material.
13. The microelectronic device package of claim 8 , further comprising a barrier material between sidewalls of the dielectric material and the metal segments located within the openings of the dielectric material.
14. The microelectronic device package of claim 8 , wherein the openings of the dielectric material comprise at least one of lines, vias, holes, or trenches.
15. The microelectronic device package of claim 8 , wherein the substrate is a silicon-less substrate comprising a printed circuit board.