Memory arrays and methods of fabricating integrated structures

1. A memory array, comprising:

a stack of alternating first and second levels;

channel material pillars extending through the stack;

vertically-stacked memory cell strings along the channel material pillars;

a common source under the stack and electrically coupled to the channel material pillars; the channel material pillars contact the common source; the common source comprising conductive protective material over and directly against metal silicide; the conductive protective material comprising a composition other than metal silicide;

wherein the conductive protective material comprises metal; and

wherein the conductive protective material comprises a plurality of discrete layers.

2. The memory array of claim 1 wherein the metal silicide comprises tungsten silicide, and wherein the conductive protective material comprises tungsten.

3. The memory array of claim 1 wherein the channel material pillars comprise silicon, and wherein silicon of the channel material pillars directly contacts metal silicide, which in turn directly contacts the conductive protective material.

4. The memory array of claim 1 wherein the channel material pillars contact the conductive protective material.

5. The memory array of claim 1 wherein at least one channel material pillar comprises a hollow structure.

6. The memory array of claim 1 wherein at least one channel material pillar comprises conductive material across an entirety of the cross section of the at least one channel material pillar.

7. A memory array, comprising:

a stack of alternating first and second levels;

channel material pillars extending through the stack, the channel material pillars comprising a hollow structure;

vertically-stacked memory cell strings along the channel material pillars;

a common source under the stack and electrically coupled to the channel material pillars;

a conductive protective material over the common source; and

wherein the channel material pillars comprise silicon directly contacting the conductive protective material.

8. The memory array of claim 7 wherein the conductive protective material comprises a plurality of discrete layers.

9. The memory array of claim 7 further comprising a metal silicide between the channel material pillars and the conductive protective material.

10. A memory array, comprising:

a stack of alternating first and second levels;

channel material pillars extending through the stack, conductive material across an entirety of the cross section of the channel material pillars;

vertically-stacked memory cell strings along the channel material pillars;

a common source under the stack and electrically coupled to the channel material pillars;

a conductive protective material over the common source; and

wherein the channel material pillars comprise silicon directly contacting the conductive protective material.

11. The memory array of claim 10 wherein the conductive protective material comprises a plurality of discrete layers.

12. The memory array of claim 10 further comprising a metal silicide between the channel material pillars and the conductive protective material.

13. A memory array, comprising:

a stack of alternating first and second levels;

channel material pillars extending through the stack;

vertically-stacked memory cell strings along the channel material pillars;

a common source under the stack and electrically coupled to the channel material pillars; the common source comprising conductive protective material over and directly against metal silicide; the conductive protective material comprising a composition other than metal silicide;

wherein the conductive protective material comprises metal; and

wherein the channel material pillars comprise silicon, and wherein silicon of the channel material pillars directly contacts metal silicide, which in turn directly contacts the conductive protective material.

14. A memory array, comprising:

a stack of alternating first and second levels;

channel material pillars extending through the stack;

vertically-stacked memory cell strings along the channel material pillars;

a common source under the stack and electrically coupled to the channel material pillars; the channel material pillars contact the common source; the common source comprising conductive protective material over and directly against metal silicide; the conductive protective material comprising a composition other than metal silicide;

wherein the conductive protective material comprises metal; and

wherein the channel material pillars comprise silicon, and wherein silicon of the channel material pillars directly contacts metal silicide, which in turn directly contacts the conductive protective material.

15. A memory array, comprising:

a stack of alternating first and second levels;

channel material pillars extending through the stack, the channel material pillars comprising a hollow structure;

vertically-stacked memory cell strings along the channel material pillars;

a common source under the stack and electrically coupled to the channel material pillars;

a conductive protective material over the common source; and

wherein the conductive protective material comprises a plurality of discrete layers.

16. A memory array, comprising:

a stack of alternating first and second levels;

channel material pillars extending through the stack, conductive material across an entirety of the cross section of the channel material pillars;

vertically-stacked memory cell strings along the channel material pillars;

a common source under the stack and electrically coupled to the channel material pillars;

a conductive protective material over the common source; and

wherein the conductive protective material comprises a plurality of discrete layers.