Apparatuses and methods to control body potential in 3D non-volatile memory operations
View Patent ↗Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
1. A system comprising:
a memory device; and
an additional device coupled to the memory device to cause the memory device to perform a memory operation, the memory device including:
a memory cell string including memory cells and a select transistor, the memory cell string including a body associated with the memory cells and the select transistor;
a control gate associated with the memory cell string;
a select gate associated with the select transistor;
a data line coupled to the body of memory cell string;
a source coupled to the body of memory cell string; and
a module configured to:
apply a first voltage having a positive value to the control gate in at least a portion of a first stage and a positive value in at least a portion of a second stage of an operation performed on a selected memory cell among the memory cells, wherein the module is configured to store information in the selected memory cell in the first stage of the operations;
apply a second voltage having a first value in at least a portion of the first stage and a second value in at least a portion of the second stage to the select gate; and
apply a third voltage having a positive value to at least one of the data line and the source in at least a portion of the second stage.
2. The system of claim 1 , wherein the additional device is external to the memory device.
3. The system of claim 1 , wherein the additional device includes a processor.
4. The system of claim 1 , wherein the additional device includes a memory controller.
5. The system of claim 1 , wherein the additional device is configured to control signals provided to the memory device to cause the memory device to perform the memory operation based on signals.
6. A system comprising:
a memory device; and
an additional device coupled to the memory device to cause the memory device to perform a memory operation, the memory device including:
a memory cell string including memory cells and a select transistor, the memory cell string including a body associated with the memory cells and the select transistor;
a control gate associated with the memory cell string;
a select gate associated with the select transistor;
a data line coupled to the body of memory cell string;
a source coupled to the body of memory cell string; and
a module configured to:
apply a first voltage having a positive value to the control gate in at least a portion of a first stage and a positive value in at least a portion of a second stage of an operation performed on a selected memory cell among the memory cells, wherein the module is configured to determine a value of information stored in the selected memory cell in the first stage of the operation;
apply a second voltage having a first value in at least a portion of the first stage and a second value in at least a portion of the second stage to the select gate; and
apply a third voltage having a positive value to at least one of the data line and the source in at least a portion of the second stage.
7. A system comprising:
a memory device; and
an additional device coupled to the memory device to cause the memory device to perform a memory operation, the memory device including:
a memory cell string including memory cells and a select transistor, the memory cell string including a body associated with the memory cells and the select transistor;
a control gate associated with the memory cell string;
a select gate associated with the select transistor;
a data line coupled to the body of memory cell string;
a source coupled to the body of memory cell string; and
a module configured to:
apply a first voltage having a positive value to the control gate in at least a portion of a first stage and a positive value in at least a portion of a second stage of an operation performed on a selected memory cell among the memory cells, wherein the module is configured to determine whether a value of information stored in the selected memory cell reaches a target value in the first stage of the operation;
apply a second voltage having a first value in at least a portion of the first stage and a second value in at least a portion of the second stage to the select gate; and
apply a third voltage having a positive value to at least one of the data line and the source in at least a portion of the second stage.
8. A system comprising:
a memory cell string including memory cells and a select transistor, the memory cell string including a body associated with the memory cells and the select transistor;
a control gate associated with the memory cell string;
a select gate associated with the select transistor;
a data line coupled to the body of memory cell string; and
a module configured to apply a voltage to the control gate in at least a portion of a first stage and in at least a portion of a second stage of an operation performed on one of the memory cells, apply a voltage having a first value in at least a portion of the first stage and a second value in at least a portion of the second stage to the select gate, the second value including a positive value, and apply a voltage having a positive value to the data line in at least a portion of the second stage.
9. The system of claim 8 , wherein the module being configured to apply a voltage to the control gate in at least a portion of a first stage and in at least a portion of a second stage comprises the module being configured to apply a voltage having a program value in the at least a portion of the first stage and being configured to apply a ground potential to the control gate during the second stage.
10. The system of claim 8 , wherein the memory cell string further includes an additional select transistor associated with the body, and an additional select gate associated with the additional select transistor, and wherein the module is configured to apply an additional voltage to the additional select gate having a first value in at least a portion of the first stage and a second value in at least a portion of the second stage.
11. A system comprising:
a memory device; and
an additional device coupled to the memory device to cause the memory device to perform a memory operation, the memory device including:
a memory cell string including memory cells, the memory cell string including a body associated with the memory cells;
a source coupled to the memory cell string;
a data line coupled to the memory cell string; and
a module configured to perform at least one of storing information in a memory cell among the memory cells and determining a value of information stored in a memory cell among the memory cells during a first time interval of an operation, to apply a voltage having a positive value to a control gate of a selected memory cell among the memory cells of the memory cell string during a second time interval of the operation, and to apply a voltage having a positive value to at least one of the source and the data line during the second time interval of the operation for controlling a potential of the body.
12. The system of claim 11 , wherein the module being configured to apply a voltage having a positive value to at least one of the source and the data line during a second time interval of the operation comprises the module being configured to induce drain leakage current in at least a portion of the body during the second time interval.
13. The system of claim 11 , wherein the module being configured to apply a voltage having a positive value to at least one of the source and the data line during a second time interval of the operation comprises the module being configured to inject holes into the body during the second time interval.
14. The system of claim 11 , wherein the module being configured to apply a voltage having a positive value to at least one of the source and the data line during a second time interval comprises the module being configured to apply a voltage having a positive value to the data line during the second time interval and to apply a voltage having a positive value to the source during the second time interval.
15. A system comprising:
a memory device; and
an additional device coupled to the memory device to cause the memory device to perform a memory operation, the memory device including:
a memory cell string including memory cells, the memory cell string including a body associated with the memory cells;
a source coupled to the memory cell string;
a data line coupled to the memory cell string; and
a module configured to perform a write stage to store information in a memory cell among the memory cells, to perform a write verify stage to determine whether a value of information stored in the memory cell reaches a target value, and to apply a voltage having a positive value to the data line during a stage between the write stage and the write verify, wherein the memory cell string is included in a select block of a memory device, and the module is configured to put a select gate in an unselected block of the memory device in a float condition.
16. The system of claim 15 , wherein the module is configured to apply a voltage having ground potential to a control gate associated with the memory cell string during the stage between the write stage and the write verify stage.
17. The system of claim 16 , wherein the memory cell string is included in a select block of a memory device, and the module is configured to put a control gate in an unselected block of the memory device in a float condition.
18. The system of claim 15 , wherein the module is configured to:
apply a voltage having a positive value to a control gate associated with the memory cell string during a first time interval of the stage between the write stage and the write verify stage; and
apply a voltage having ground potential to the control gate during a second time interval of the stage between the write stage and the write verify stage.
19. The system of claim 15 , wherein the module is configured to:
apply a voltage having a positive value to a select gate associated with a select transistor of the memory cell string during a first time interval of the stage between the write stage and the write verify stage; and
apply a voltage having ground potential to the select gate during a second time interval of the stage between the write stage and the write verify stage.