IP Library Granted Patent US 11,552,552
Granted Patent B2
US 11,552,552 · App. 15/918,960 · Granted Jan 10, 2023

Power management integrated circuit with bleed circuit control

Inventor: Matthew David Rowley (Boise, ID)
Assignee: Micron Technology, Inc.
H02M1/32G06F1/305G11C5/14H01L23/49838H01L23/50H02M1/322H02M3/33507
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Quick Facts
Patent No.
US 11,552,552
App. No.
15/918,960
Granted
Jan 10, 2023
Kind
B2
Abstract

A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.

Claims (33)

1. A power management integrated circuit, comprising:

a voltage regulator to generate an output voltage; and

bleed circuit, coupled to the voltage regulator, that is activated during a shutdown process to reduce the output voltage and prevent restarting of the output voltage, wherein the bleed circuit comprises a comparator to generate an output from comparing the output voltage and a programmable threshold;

wherein the output controls engagement of the bleed circuit during the shutdown process;

wherein when the output voltage is higher than the threshold during the shutdown process, the output of the comparator causes the bleed circuit to engage in reducing the output voltage, and the comparator prevents the voltage regulator from restarting and powering up the output voltage;

wherein when the output voltage is higher than the threshold during the shutdown process, the output of the comparator prevents the sequencer from restarting from the shutdown process;

wherein the threshold is programmed into the power management integrated circuit before the power management integrated circuit is connected to the non-volatile memory in the memory system.

2. The power management integrated circuit of claim 1 , wherein the bleed circuit comprises a resistor coupled to a switch controlled by the output.

3. The power management integrated circuit of claim 1 , wherein when the output voltage is no longer higher than the threshold during the shutdown process, the output of the comparator allows the voltage regulator to restart.

4. The power management integrated circuit of claim 3 , wherein when the output voltage is no longer higher than the threshold during the shutdown process, the output of the comparator allows a sequencer to restart, wherein the sequencer controls a sequence of operations involving at least the voltage regulator.

5. The power management integrated circuit of claim 4 , wherein when the output voltage is no longer higher than the threshold during the shutdown process, the output of the comparator causes the bleed circuit to disengage from reducing the output voltage.

6. The power management integrated circuit of claim 4 , wherein when the output voltage is no longer higher than the threshold during the shutdown process, the output of the comparator causes the bleed circuit to disengage from reducing the output voltage during restart after the shutdown process.

7. A memory system having a power management integrated circuit of claim 1 , further comprising:

a non-volatile memory powered by the output voltage.

8. A method implemented in a power management integrated circuit, the method comprising:

generating, using a voltage regulator of the power management integrated circuit, an output voltage; and

during a shutdown process:

activating a bleed function of the power management integrated circuit; and

reducing the output voltage using the bleed function, wherein when the bleed function is activated:

comparing the output voltage to a threshold;

generating an output from the comparing; and

allowing or preventing restart of the output voltage based on the output generated from the comparing;

deactivating the bleed function in response to the output voltage being lower than the threshold; and

receiving from outside of the power management integrated circuit, and storing the threshold for the comparing;

wherein the threshold is programmed into the power management integrated circuit before the power management integrated circuit is connected to the non-volatile memory in the memory system.

9. The method of claim 8 , wherein the bleed function remains activated while the output voltage is higher than the threshold during the shutdown process.

10. A method, comprising:

programming into a power management integrated circuit a threshold according to a voltage requirement of a non-volatile memory; and

coupling the power management integrated circuit and the non-volatile memory in a memory system;

wherein:

during a normal operation of the memory system, the power management integrated circuit generates and supplies a voltage to the non-volatile memory; and

during a shutdown process of the memory system, a bleed function of the power management integrated circuit reduces the voltage below the threshold before allowing restart of the memory system;

wherein the threshold is programmed into the power management integrated circuit after the power management integrated circuit and the non-volatile memory are assembled in the memory system.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0965 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2018
From: ROWLEY, MATTHEW DAVID
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047057/0032 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 8 TO PATENT SECURITY AGREEMENT Recorded May 7, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 046084/0955 →