Apparatuses and methods for data transfer from sensing circuitry to a controller
The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.
1. An apparatus, comprising:
a memory device, comprising:
an array of memory cells; and
an operation manager associated with a register file, the operation manager located in a controller of the array and selectably coupled to the array via a latch component, the operation manager configured to:
execute a first command from the controller to transfer a register value via the latch component to the register file associated with the operation manager;
issue a second command to fetch circuitry in the controller configured to direct a retrieval of the register value to a plurality of latches of the latch component;
selectably transfer from the plurality of latches a stored register value, retrieved by the fetch circuitry, as data values input to a plurality of data lines via a multiplexer to select a latch of the plurality of latches to couple to a shared I/O line; and
store the transferred register value in the register file to be provided for execution of a received set of instructions to perform an operation.
2. The apparatus of claim 1 , wherein the apparatus further comprises the plurality of latches in the latch component configured to selectably transfer cached data sensed from a particular row of memory cells by being selectably coupled to a data line.
3. The apparatus of claim 1 , wherein:
the operation manager provides the stored register value for execution of a set of instructions received from a host; and
wherein the set of instructions is executed without an additional retrieval operation for the register value in the array.
4. An apparatus, comprising:
a memory device, comprising:
an array of memory cells; and
an operation manager associated with a register file, the operation manager located in a controller of the array and selectably coupled to the array via a latch component, the operation manager configured to:
execute a first command from the controller to transfer a register value via the latch component to the register file associated with the operation manager; and
issue a second command to fetch circuitry in the controller configured to direct a retrieval of the register value to a plurality of latches of the latch component; wherein:
the operation manager directs fetch circuitry in the controller to execute a fetch operation for the register value from a particular row of the array; and
the operation manager is selectably coupled to the plurality of latches for the transfer of the register value to the register file.
5. An apparatus, comprising:
a memory device, comprising:
an array of memory cells; and
an operation manager associated with a register file, the operation manager located in a controller of the array and selectably coupled to the array via a latch component, the operation manager configured to:
execute a first command from the controller to transfer a register value via the latch component to the register file associated with the operation manager; and
issue a second command to fetch circuitry in the controller configured to direct a retrieval of the register value to a plurality of latches of the latch component; wherein:
the array includes a column of memory cells having a pair of complementary sense lines; and
the latch component comprises a latch selectably coupled to each of the pair of complementary sense lines.