Apparatuses and methods for comparing data patterns in memory

1. A method for comparing data patterns, comprising:

comparing, in sensing circuitry, a number of stored data patterns stored in a memory array to a target data pattern by performing a number of iterative operation phases comprising a number of logical operations using a sense amplifier and a compute component of the sensing circuitry, wherein a result from performing a first of the number of iterative operation phases is used as an input into a second of the number of iterative operation phases,

wherein at least one of the number of logical operations is performed without transferring data from the memory array via an input/output (I/O) line; and

determining whether a stored data pattern of the number of stored data patterns matches the target data pattern.

2. The method of claim 1 , wherein determining whether the stored data pattern of the number of stored data patterns matches the target data pattern comprises determining whether the stored data pattern of the number of stored data patterns matches the target data pattern without transferring data via a sense line address access for at least one of the number of logical operations.

3. The method of claim 1 , wherein comparing the number of stored data patterns stored in the memory array to the target data pattern comprises performing a particular number of operations of the number of logical operations using the sensing circuitry, wherein the particular number of operations is based on a number of data units of the target data pattern.

4. The method of claim 1 , wherein an amount of time to compare the number of stored data patterns stored in the memory array to the target data pattern is independent of the number of stored data patterns.

5. The method of claim 1 , wherein:

the number of stored data patterns each comprise a plurality of data units, and

each of the plurality of data units of a particular one of the number of stored data patterns is stored in a different memory cell coupled to a same sense line of the array.

6. The method of claim 5 , wherein a first data unit of the plurality of data units of each of the number of stored data patterns is stored in a respective memory cell coupled to a first access line of the array and a second data unit of each of the number of stored data patterns is stored in a respective memory cell coupled to a second access line.

7. The method of claim 1 , wherein comparing the number of stored data patterns comprises comparing a data value of each data unit of the stored data patterns stored in memory cells coupled to an access line to a first data value of the target data pattern.

8. The method of claim 7 , wherein the first data value comprises a “0”.

9. The method of claim 7 , wherein the access line corresponds to a data unit of the target data pattern having the first data value.

10. The method of claim 9 , comprising repeating comparisons of data values of data units stored in memory cells coupled to additional access lines of the memory array that correspond to data units of the target data pattern that have the first data value.

11. The method of claim 10 , comprising accumulating values from the repeated comparisons in sensing circuitry coupled to the memory array.

12. The method of claim 11 , comprising inverting the accumulated values in sensing circuitry coupled to the memory array.

13. The method of claim 12 , wherein comparing the number of stored data patterns comprises comparing a data value of each data unit of the stored data patterns stored in memory cells coupled to another access line to a second data value of the target data pattern that is different than the first data value.

14. The method of claim 13 , wherein the second data value comprises a “1”.

15. The method of claim 13 , wherein comparing the number of stored data patterns comprises comparing a data value of each data unit stored in memory cells coupled to another additional access line that corresponds to a data unit of the target data pattern that has the second data value.

16. The method of claim 13 , comprising repeating comparisons of data values of data units of the stored data patterns stored in memory cells coupled to other additional access lines of the memory array that correspond to data units of the target data pattern that have the second data value.

17. An apparatus, comprising:

an array of memory cells configured to store a plurality of stored data patterns; and

a controller configured to operate sensing circuitry coupled to the array to:

compare a target data pattern to the plurality of stored data patterns stored in the array by performing a number of iterative operation phases comprising a number of logical operations using a sense amplifier and a compute component of the sensing circuitry, wherein a result from performing a first of the number of iterative operation phases is used as an input into a second of the number of iterative operation phases;

wherein at least one of the number of logical operations are performed without transferring data from the array via an input/output (I/O) line; and

determine whether one or more stored data pattern of the plurality of stored data patterns matches the target data pattern.

18. The apparatus of claim 17 , wherein the controller is configured to operate the sensing circuitry to compare the target data pattern to the plurality of stored data patterns, in parallel, via execution of a quantity of compare operations, and wherein the quantity of compare operations is equal to a quantity of data units corresponding to the plurality of stored data patterns.

19. A system, comprising:

a host; and

a memory device coupled to the host and configured to compare, in parallel, a target data pattern to a plurality of stored data patterns stored in an array of the memory device by:

performing, at most, N compare operations, wherein N is a quantity of data units of the plurality of stored data patterns, and wherein the quantity of compare operations is independent of the quantity of stored data patterns being compared to the target data pattern;

performing a number of iterative operation phases comprising a number of logical operations per compare operation using a sense amplifier and a compute component of sensing circuitry, wherein a result from performing a first of the number of iterative operation phases is used as an input into a second of the number of iterative operation phases;

wherein at least one of the number of logical operations is performed without transferring data from the array to the host via an input/output (I/O) line; and

determining whether one or more of the plurality of stored data patterns matches the target data pattern.

20. The system of claim 19 , wherein the host comprises a processing resource external to the memory device.