IP Library Granted Patent US 10,304,499
Granted Patent B2
US 10,304,499 · App. 15/900,553 · Granted May 28, 2019

Power delivery circuitry

Inventor: Shaun Alan Stickel (Boise, ID)
Assignee: Micron Technology, Inc.
G11C5/141G11C5/143G11C7/24G11C14/00G11C16/30
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Quick Facts
Patent No.
US 10,304,499
App. No.
15/900,553
Granted
May 28, 2019
Kind
B2
Abstract

A memory device may include a memory system and an energy storage device. Additionally, the energy storage device may supply a first power to the memory system when a second power from a power supply is eliminated or insufficient. A method of operation may include receiving, in power delivery circuitry, a first power from a power supply. The method may further include charging an energy storage device disposed within a computer component. The method may also include receiving, in the power delivery circuitry, a second power from the energy storage device when the first power is insufficient. The method may further include delivering a third power, via the power delivery circuitry, to a memory system of the computer component.

Claims (29)

1. A memory device, comprising:

a memory system; and

an energy storage device, wherein the energy storage device is configured to supply a first power to the memory system when a second power from a power supply is eliminated or insufficient.

2. The system of claim 1 , wherein the memory device comprises power delivery circuitry configured to deliver the first power, the second power, or a combination thereof to the memory system.

3. The system of claim 2 , wherein the power delivery circuitry comprises one or more switches to couple or decouple the first power or the second power to the memory system.

4. The system of claim 1 , wherein the second power is insufficient if a power demand of the energy storage device is greater than a maximum power of the power supply.

5. The system of claim 4 , wherein the memory system is configured to maintain a lower latency when the power demand of the memory system is greater than the maximum power of the power supply than when the power demand of the memory system is less than the maximum power of the power supply.

6. The system of claim 1 , wherein the energy storage device is configured to be charged via the power supply.

7. The system of claim 1 , wherein the energy storage device is configured to be charged relative to ground.

8. The system of claim 7 , wherein the energy storage device is configured to discharge by disconnecting a first electrode of the energy storage device from ground and connecting the first electrode to an output of a power delivery circuit, wherein a second electrode of the energy storage device is configured to be connected to an input of the power delivery circuit.

9. The system of claim 8 , wherein the power delivery circuit regulates the voltage to the memory system.

10. A method comprising:

receiving, in power delivery circuitry, a first power from a power supply;

charging an energy storage device disposed within a computer component;

receiving, in the power delivery circuitry, a second power from the energy storage device when the first power is insufficient; and

delivering a third power, via the power delivery circuitry, to a memory system of the computer component.

11. The method of claim 10 , wherein the third power comprises a combination of the first power and the second power.

12. The method of claim 10 , wherein the computer component is a memory device.

13. The method of claim 12 , wherein the memory device comprises a solid state memory device.

14. The method of claim 10 , wherein the computer component is a computer motherboard.

15. The method of claim 10 , wherein the computer component is a video card.

16. The method of claim 10 , wherein the energy storage device is a capacitor or a battery.

17. A computer component comprising:

a memory system;

an energy storage device; and

power delivery circuitry, wherein the power delivery circuitry is configured to receive a first power from an power supply and a second power from the energy storage device, wherein the power delivery circuitry is configured to supply a third power to the memory system, wherein the third power comprises the first power, the second power, or a combination thereof.

18. The computer component of claim 17 , wherein the computer component is a motherboard, a video card, or a memory device.

19. The computer component of claim 17 , wherein if a power demand of the computer component is greater than a maximum output of the power supply, the power delivery circuitry is configured to satisfy the power demand by combining the first power and the second power.

20. The computer component of claim 19 , wherein the performance of the memory system or the computer component as a whole is improved or maintained by combining the first power and the second power.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0965 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 8 TO PATENT SECURITY AGREEMENT Recorded May 7, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 046084/0955 →
Continuity (3)
Continuation 15665062 · Jul 31, 2017
Continuation 15169075 · May 31, 2016
Related Publication 20180174622A1 · Jun 21, 2018