Hardware-based power management integrated circuit register file write protection
Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.
1. A device comprising:
a register file comprising a plurality of a registers each of the registers storing multiple bits of fixed-length data, at least one register in the register file containing a write register bit (WRB) located at a position of a pre-configured bit of the at least one register, the remaining bits other than the pre-configured bit storing data, the WRB bit hardwired to a write-enable of the register file; and
an interface configured to receive messages from a host application, the messages including a WRB enablement signal, the WRB enablement signal including a bit string identifying the least one register and the position of the pre-configured bit,
wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.
2. The device of claim 1 , the register file further comprising a write enable and the WRB being hardwired to the write enable.
3. The device of claim 1 , further comprising one or more switch drivers, voltage regulators and a sequencer, the switch drivers, voltage regulators and a sequencer controlled by values stored in the register file.
4. The device of claim 1 , the interface configured to receive messages from the host application over an I2C bus.
5. The device of claim 1 , the WRB comprising a first or last bit of a designated register.
6. The device of claim 1 , wherein receiving a stop bit over the interface comprises receiving a second write request from the host application, the second write request toggling the value of the WRB.
7. The device of claim 1 , wherein receiving a stop bit over the interface comprises receiving a stop bit over the interface immediately after writing a first message to the register file.
8. The device of claim 1 , wherein receiving a stop bit over the interface comprises receiving a stop bit over the interface after writing multiple messages to the register file.
9. The device of claim 1 , the least one register comprising data encoded using a linear block code.
10. A method comprising:
receiving, at a power management integrated circuit (PMIC), a write register bit (WRB) enablement signal, the WRB enablement signal including a bit string identifying a designated register and a position of a pre-configured bit;
enabling, by the PMIC, a write mode of a register file in the PMIC each of the registers in the register file storing multiple bits of fixed-length data, the enabling comprising setting a WRB in the designated register of the register file, the WRB located at the position of the pre-configured bit of the designated register, the remaining bits of the designated register other than the pre-configured bit storing data, the WRB bit hardwired to a write-enable of the register file;
receiving, by the PMIC, a write request;
writing, by the PMIC, data included in the write request to a register in the register file;
receiving, by the PMIC, a stop bit; and
disabling, by the PMIC, the write mode of the register file in the PMIC.
11. The method of claim 10 , further comprising initializing the WRB upon startup of the PMIC.
12. The method of claim 10 , the enabling the write mode of a register file in the PMIC comprising automatically enabling the write mode when the WRB is set.
13. The method of claim 10 , the receiving a write register bit (WRB) enablement signal comprising receiving the WRB enablement signal over an I2C bus.
14. The method of claim 10 , the enabling the write mode of a register file in the PMIC comprising enabling a first or last bit of the designated register.
15. The method of claim 10 , the receiving a stop bit comprising receiving a stop bit immediately after writing a first message to the register file.
16. The method of claim 10 , the receiving a stop bit over comprising receiving a stop bit after writing multiple messages to the register file.
17. The method of claim 10 , further comprising:
receiving, by the PMIC, a second write request;
determining, by the PMIC, if the register file is in write mode; and
selectively ignoring, by the PMIC, the second write request if the register file is not in write mode.
18. The method of claim 17 , the selectively ignoring further comprising setting a counter to disable further write requests for a predefined number of clock cycles.