Power management integrated circuit with in situ non-volatile programmability

1. A power management integrated circuit (PMIC) comprising:

a first one-time programmable (OTP) memory bank;

a second OTP memory bank, wherein the first OTP memory bank

comprises a first bit, the first bit controlling write access to the second OTP memory bank, the first bit being hardwired to a write enable of the second OTP memory bank; and

access control logic, communicatively coupled to the first OTP memory bank and the second OTP memory bank, the access control logic configured to:

utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty,

write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and

utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.

2. The PMIC of claim 1 , wherein the first OTP memory bank is pre-programmed prior to use and the second OTP memory bank is empty prior to use.

3. The PMIC of claim 1 , the access control logic further configured to select between the first OTP memory bank and the second OTP memory bank after a power cycle.

4. The PMIC of claim 1 , the access control logic further configured to ignore the write request if the second OTP memory bank is not empty.

5. The PMIC of claim 1 , further comprising an interface configured to receive the write request over a bus.

6. The PMIC of claim 5 , the write request conforming to an I2C protocol message.

7. The PMIC of claim 1 , further comprising at least one of switch driver, a voltage regulator, or a sequencer.

8. The PMIC of claim 1 , further comprising a switch driver, the switch driver configured to drive a solid-state storage device.

9. A method comprising:

determining, by a power management integrated circuit (PMIC), whether a second one-time programmable (OTP) memory bank contains data;

utilizing, by the PMIC, a first OTP memory bank as a parameter source if the second OTP memory bank does not contain data;

enabling, by the PMIC, write access to the second OTP memory bank by writing to a first bit in the first OTP memory bank, the first bit being hardwired to a write enable of the second OTP memory bank;

writing, by the PMIC, data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty; and

utilizing, by the PMIC, the second OTP memory bank as a parameter source if the second OTP memory bank does contain data.

10. The method of claim 9 , the determining whether the second OTP memory bank contains data performed in response to powering on the PMIC.

11. The method of claim 10 , the powering on the PMIC resulting from a power cycle.

12. The method of claim 9 , the writing data to the second OTP memory bank performed upon determining that writing is enabled for the second OTP memory bank.

13. The method of claim 12 , the determining that writing is enabled for the second OTP memory bank comprising analyzing the write enable of the second OTP memory bank.

14. The method of claim 9 , the utilizing the first OTP memory bank as a parameter source and utilizing the second OTP memory bank as a parameter source both comprising supply parameters from a respective memory bank to circuitry of the PMIC.

15. The method of claim 9 , further comprising pre-programming the first OTP memory bank prior to use.

16. The method of claim 15 , the second OTP memory bank being uninitialized prior to use.

17. The method of claim 9 , further comprising ignoring the write request if data is stored in the second OTP memory bank.

18. The method of claim 9 , further comprising receiving the write request from the host application over a bus.