Integrated structures and methods of forming vertically-stacked memory cells
View Patent ↗Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.
1. An integrated structure, comprising:
a stack of alternating dielectric levels and conductive levels;
memory cells within the conductive levels;
an insulative material over the stack;
a select gate material over the insulative material;
an opening extending through the select gate material, through the insulative material, and through the stack of alternating dielectric levels and conductive levels; a first region of the opening within the insulative material being wider along a cross-section than a second region of the opening within the select gate material, and being wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels;
channel material within the opening and adjacent the insulative material, the select gate material and the memory cells;
cavities extending into the conductive levels;
charge-blocking material and charge-storage structures within the cavities; and
wherein the memory cells include the charge-blocking material and charge-storage structures.
2. The integrated structure of claim 1 wherein the insulative material comprises silicon dioxide.
3. The integrated structure of claim 1 wherein the select gate material is drain-side select gate material and comprises conductively-doped silicon.
4. The integrated structure of claim 1 wherein the second and third regions of the opening are about a same width as one another along the cross-section.
5. The integrated structure of claim 1 wherein the conductive levels comprise conductively-doped silicon.
6. The integrated structure of claim 1 comprising oxide between the select gate material and the channel material.
7. The integrated structure of claim 1 wherein the insulative material is a third insulative material; wherein a first insulative material is over the stack, a second insulative material is over the first insulative material, and the third insulative material is over the second insulative material.
8. The integrated structure of claim 7 wherein the first, second and third insulative materials comprise silicon dioxide, silicon nitride and silicon dioxide, respectively.
9. The integrated structure of claim 1 wherein the opening extends through a source-side select gate material and to a conductive source material, and wherein the first region of the opening is wider than a fourth region of the opening within the source-side select gate material along the cross-section.
10. An integrated structure, comprising:
a conductive source material over a semiconductor substrate;
a source-side select gate material over the conductive source material;
a stack of alternating dielectric levels and conductive levels over the source-side select gate material;
memory cells within the conductive levels;
an insulative material over the stack;
a drain-side select gate material over the insulative material;
an opening extending through the drain-side select gate material, through the insulative material, and through the stack of alternating dielectric levels and conductive levels, through the source-side select gate material and to the conductive source material; a first region of the opening within the insulative material being wider along a cross-section than a second region of the opening within the select gate material, and being wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels;
channel material within the opening and adjacent the insulative material, the select gate material and the memory cells;
cavities extending into the conductive levels;
charge-blocking material and charge-storage structures within the cavities; and
wherein the memory cells include the charge-blocking material and charge-storage structures.
11. The integrated structure of claim 10 wherein the first region of the opening is wider than a fourth region of the opening within the source-side select gate material along the cross-section.
12. The integrated structure of claim 10 wherein the charge-storage structures comprise floating gate material.
13. The integrated structure of claim 10 wherein the charge-storage structures comprise charge-trapping material.