IP Library Granted Patent US 10,290,581
Granted Patent B2
US 10,290,581 · App. 15/916,575 · Granted May 14, 2019

Methods of forming conductive structures including stair step or tiered structures having conductive portions

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Quick Facts
Patent No.
US 10,290,581
App. No.
15/916,575
Granted
May 14, 2019
Kind
B2
Abstract

Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

Claims (39)

1. A method of forming a conductive structure, the method comprising:

forming openings through a stack of material at a landing of the conductive structure defined directly between two stair step structures, the two stair step structures being positioned on one side of and in electrical communication with a semiconductor device;

forming contacts in the openings in the stack of the material at the landing; and

electrically coupling a conductive portion of at least one step of each of the two stair step structures with at least one contact of the contacts at the landing.

2. The method of claim 1 , further comprising forming the stack of material with alternating insulative and conductive materials.

3. The method of claim 2 , further comprising forming a liner in each opening of the openings to surround a contact therein.

4. The method of claim 1 , further comprising forming the stack of material with alternating insulative materials comprising a first insulative material and a second sacrificial insulative material.

5. The method of claim 4 , further comprising:

forming an opening through the stack of material;

removing a portion of the second sacrificial insulative material adjacent the opening in a volume of the second sacrificial material underlying the first insulative material; and

depositing a conductive material in the opening and in the volume from which the portion of the second sacrificial material is removed to form the conductive portion of at least one step of the stair step structure.

6. The method of claim 5 , further comprising:

removing a portion of the conductive material within the opening; and

depositing another insulative material within the opening.

7. The method of claim 6 , further comprising forming an electrical connection between the conductive portion of at least one step of the stair step structure and another, adjacent conductive portion of the at least one step around the another insulative material.

8. The method of claim 1 , further comprising performing a replacement gate process on at least one stair step structure of the stair step structures while masking the landing of the conductive structure.

9. The method of claim 1 , further comprising electrically connecting the conductive structure to an array of memory cells.

10. A method of forming a conductive structure, the method comprising:

defining stair step structures along a length of the conductive structure, each stair step structure comprising at least two conductive steps;

at least partially separating each conductive step of the at least two conductive steps from an adjacent conductive step of the at least two conductive steps with insulative material;

separating a first stair step structure of the stair step structures and a second stair step structure of the stair step structures along the length of the conductive structure with at least one landing comprising at least one via extending through the conductive structure; and

connecting a conductive portion of one conductive step of the at least two conductive steps of the stair step structures and the at least one via extending through the conductive structure with an access line.

11. The method of claim 10 , further comprising electrically connecting the at least two conductive steps to an array of electronic circuits.

12. A method of forming a conductive structure of a semiconductor device, the method comprising:

defining tiered structures along a length of the conductive structure, each tiered structure comprising at least two tiers having a conductive portion;

at least partially separating each conductive portion of the at least two tiers from an adjacent conductive portion of the at least two tiers with insulative material; and

positioning a landing comprising vias extending through the conductive structure at the landing, the landing positioned between a first tiered structure of the tiered structures and a second tiered structure of the tiered structures.

13. The method of claim 12 , further comprising coupling conductive portions of the at least two tiers of the tiered structures to a respective via of the vias with access lines.

14. The method of claim 12 , further comprising extending access lines from one conductive portion, over a respective tier of the at least two tiers, and to at least one of the vias extending through the conductive structure.

15. The method of claim 12 , further comprising:

extending stack slot elements along the length of the conductive structure; and

extending at least one stack slot element of the stack slot elements discontinuously along the length of the conductive structure.

16. The method of claim 15 , further comprising at least partially physically and electrically separating at least one tier of a tiered structure of the tiered structures into a first sub-tier portion and a second sub-tier portion with the at least one discontinuous stack slot element.

17. The method of claim 16 , further comprising defining a short in the at least one tier along an end of the at least one discontinuous stack slot element to electrically connect the first sub-tier portion and the second sub-tier portion.

18. The method of claim 15 , further comprising positioning the at least one discontinuous stack slot element laterally within one tiered structure of the tiered structures separated from lateral sides of the conductive structure.

19. The method of claim 15 , further comprising:

extending at least another stack slot element of the stack slot elements continuously along the length of the conductive structure; and

defining at least a portion of a lateral side of the conductive structure with the at least one continuous stack slot element.

20. The method of claim 12 , further comprising electrically connecting the conductive portion of the at least two tiers to a word line driver.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0965 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 8 TO PATENT SECURITY AGREEMENT Recorded May 7, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 046084/0955 →