Bypassed gate transistors having improved stability
A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.
1. A transistor, comprising:
a first drain finger and a second drain finger that each have a longitudinal axis that extends in a first direction, the first and second drain fingers separated from one another in a second direction that is perpendicular to the first direction; and
wherein a first end of the first drain finger and a first end of the second drain finger define a first axis, a second end of the first drain finger and a second end of the second drain finger define a second axis, and an odd mode resistor is physically positioned within a rectangle defined by the first drain finger, the second drain finger, the first axis and the second axis when the transistor is viewed from above.
2. The transistor of claim 1 , further comprising a source contact that has a longitudinal axis that extends in the first direction, the source contact comprising first and second discontinuous source contact segments, the source contact positioned between the first and second drain fingers, wherein the odd mode resistor is in between the first and second discontinuous source contact segments.
3. The transistor of claim 2 , further comprising:
a gate finger that has a longitudinal axis that extends in the first direction, the gate finger positioned between the first drain finger and the source contact; and
a gate jumper that has a longitudinal axis that extends in the first direction,
wherein the gate jumper is electrically connected to the gate finger through a gate resistor.
4. The transistor of claim 3 , wherein the gate jumper extends above the source contact.
5. The transistor of claim 2 , further comprising a gate signal distribution bar in a gap between the first and second discontinuous source contact segments.
6. A transistor, comprising:
a first gate finger that comprises at least a first gate finger segment and a second gate finger segment that is colinear with the first gate finger segment;
a first gate resistor physically positioned between the first gate finger segment and the second gate finger segment;
a second gate finger that comprises at least a third gate finger segment and a fourth gate finger segment that is colinear with the third gate finger segment;
a second gate resistor physically positioned between the third gate finger segment and the fourth gate finger segment,
wherein the second gate finger segment is electrically connected to the fourth gate finger segment through an odd mode resistor.
7. The transistor of claim 6 , further comprising:
a gate bus; and
a gate jumper that electrically connects the gate bus to the second gate finger segment through the first gate resistor.
8. The transistor of claim 6 , further comprising a gate signal distribution bar, wherein the odd mode resistor is interposed along the gate signal distribution bar.
9. The transistor of claim 6 , further comprising a source contact that is positioned between the first gate finger and the second gate finger, the source contact comprising first and second discontinuous source contact segments, wherein the odd mode resistor is in between the first and second discontinuous source contact segments.
10. A transistor comprising:
a first gate finger and a second gate finger that each have a longitudinal axis that extends in a first direction, the first and second gate fingers separated from one another in a second direction that is perpendicular to the first direction;
a first gate jumper having a longitudinal axis extending in the first direction,
a second gate jumper having a longitudinal axis extending in the first direction,
a first gate signal distribution bar that electrically connects the gate jumper to the first gate finger;
a second gate signal distribution bar that electrically connects the second gate jumper to the second gate finger; and
an odd mode resistor interposed between the first gate signal distribution bar and the second gate signal distribution bar.
11. The transistor of claim 10 , further comprising a source contact that extends in the first direction, wherein the gate jumper extends above the source contact.
12. The transistor of claim 11 , wherein the source contact includes a plurality of discontinuous source contact segments that are electrically connected to each other, and wherein the odd mode resistor is positioned in a gap between two adjacent ones of the source contact segments.
13. The transistor of claim 10 , further comprising a gate bus that extends in the second direction, the gate bus electrically connected to the first and second gate fingers.
14. The transistor of claim 13 , wherein the first gate finger comprises discontinuous first and second gate finger segments, and a first gate resistor is coupled between the gate bus and the first gate finger segment and a second gate resistor is coupled between the gate bus and the second gate finger segment.
15. The transistor of claim 14 , wherein the first gate resistor is positioned in a gap between the first and second gate finger segments.
16. The transistor of claim 14 , wherein the first gate jumper is coupled to the second gate finger segment through the second gate resistor.
17. The transistor of claim 14 , wherein the second gate resistor is farther from the gate bus than is the first gate finger segment.
18. The transistor of claim 14 , wherein the second gate resistor is farther from the gate bus than is the first gate resistor.
19. The transistor of claim 14 , wherein the second gate finger comprises discontinuous third and fourth gate finger segments, and a third gate resistor is coupled between the gate bus and the third gate finger segment and a fourth gate resistor is coupled between the gate bus and the fourth gate finger segment.
20. The transistor of claim 19 , wherein the first gate signal distribution bar is electrically interposed between the first gate jumper and the second gate finger segment and is electrically interposed between the first gate jumper and the fourth gate finger segment.
21. A transistor comprising:
a first group of segmented gate fingers, where a first of the gate fingers in the first group comprises a first gate finger segment and a second gate finger segment;
a first lossy element positioned adjacent the first gate finger segment and a second lossy element positioned adjacent the second gate finger segment;
a first gate signal distribution bar that is between the first gate finger segment and the second gate finger segment;
a second group of segmented gate fingers, where a first of the gate fingers in the second group comprises a third gate finger segment and a fourth gate finger segment;
a third lossy element positioned adjacent the fourth gate finger segment;
a second gate signal distribution bar that is between the third gate finger segment and the fourth gate finger segment; and
a fourth lossy element that electrically connects the first gate signal distribution bar to the second gate signal distribution bar.
22. The transistor of claim 21 , further comprising a gate bus, wherein the third gate finger segment is closer to the gate bus than the fourth gate finger segment.
23. The transistor of claim 21 , wherein the first lossy element is also positioned adjacent the third gate finger segment.
24. The transistor of claim 21 , wherein the first lossy element comprises a first gate resistor, the second lossy element comprises a second gate resistor, the third lossy element comprises a third gate resistor, and the fourth lossy element comprises an odd mode resistor.
25. The transistor of claim 21 , wherein the first group of gate fingers comprises at least four gate fingers, and the second group of gate fingers comprises at least four gate fingers.
26. The transistor of claim 21 , wherein the first and second gate finger segments and the second lossy element are all colinear with each other, and the third and fourth gate finger segments and the third lossy element are all colinear with each other.
27. The transistor of claim 26 , wherein the first lossy element is positioned in between a first longitudinal axis of the first of the gate fingers in the first group and a second longitudinal axis of the first of the gate fingers in the second group.