Passive discharge circuit for bidirectional semiconductor switches
A semiconductor device includes: a semiconductor body having an active region and a substrate region beneath the active region; a bidirectional switch having first and second gate structures configured to control a conductive state of a channel in the active region, and first and second input-output terminals electrically connected to the channel; and a passive discharge circuit in parallel with the bidirectional switch and configured to utilize a fraction of a voltage across the first and second input-output terminals to switch on a transistor device that electrically connects the substrate region to the input-output terminal at the lower potential during an off-state of the bidirectional switch and during ZVS (zero-voltage switching) transition periods.
1. A semiconductor device, comprising:
a semiconductor body comprising an active region and a substrate region beneath the active region;
a bidirectional switch comprising first and second gate structures configured to control a conductive state of a channel in the active region, and first and second input-output terminals electrically connected to the channel;
a first passive cascode circuit configured to block a voltage between the first input-output terminal and the substrate region and activate a discharge path between the substrate region and the second input-output terminal, when the bidirectional switch is in an off-state and the first input-output terminal is at a higher potential than the second input-output terminal; and
a second passive cascode circuit configured to block a voltage between the second input-output terminal and the substrate region and activate a discharge path between the substrate region and the first input-output terminal, when the bidirectional switch is in the off-state and the second input-output terminal is at a higher potential than the first input-output terminal.
2. The semiconductor device of claim 1 , wherein:
the discharge path between the substrate region and the first input-output terminal comprises a first normally-off transistor having a source electrically connected to the substrate region, a drain electrically connected to the first input-output terminal, and a gate electrically connected to the second passive cascode circuit; and
the discharge path between the substrate region and the second input-output terminal comprises a second normally-off transistor having a source electrically connected to the substrate region, a drain electrically connected to the second input-output terminal, and a gate electrically connected to the first passive cascode circuit.
3. The semiconductor device of claim 2 , wherein:
the first passive cascode circuit is configured to provide a voltage for the gate of the second normally-off transistor when the bidirectional switch is in the off-state and the first input-output terminal is at a higher potential than the second input-output terminal, and comprises a first step-down circuit configured to reduce the voltage applied to the gate of the second normally-off transistor; and
the second passive cascode circuit is configured to provide a voltage for the gate of the first normally-off transistor when the bidirectional switch is in the off-state and the second input-output terminal is at a higher potential than the first input-output terminal, and comprises a second step-down circuit configured to reduce the voltage applied to the gate of the first normally-off transistor.
4. The semiconductor device of claim 1 , wherein:
the first passive cascode circuit comprises a first normally-on transistor having a source that controls the discharge path between the substrate region and the second input-output terminal, a drain electrically connected to the first input-output terminal, and a gate electrically connected to the substrate region, and a first normally-off transistor having a source electrically connected to the substrate region, a drain electrically connected to the source of the first normally-on transistor, and a gate electrically connected to the second passive cascode circuit or the substrate region; and
the second passive cascode circuit comprises a second normally-on transistor having a source that controls the discharge path between the substrate region and the first input-output terminal, a drain electrically connected to the second input-output terminal, and a gate electrically connected to the substrate region, and a second normally-off transistor having a source electrically connected to the substrate region, a drain electrically connected to the source of the second normally-on transistor, and a gate electrically connected to the first passive cascode circuit or the substrate region.
5. The semiconductor device of claim 4 , wherein:
the discharge path between the substrate region and the first input-output terminal comprises a third normally-off transistor having a source electrically connected to the substrate region, a drain electrically connected to the first input-output terminal, and a gate electrically connected to the source of the second normally-on transistor; and
the discharge path between the substrate region and the second input-output terminal comprises a fourth normally-off transistor having a source electrically connected to the substrate region, a drain electrically connected to the second input-output terminal, and a gate electrically connected to the source of the first normally-on transistor.
6. The semiconductor device of claim 5 , wherein:
the first passive cascode circuit is configured to provide a voltage for the gate of the fourth normally-off transistor when the bidirectional switch is in the off-state and the first input-output terminal is at a higher potential than the second input-output terminal, and comprises a first step-down circuit configured to reduce the voltage applied to the gate of the fourth normally-off transistor; and
the second passive cascode circuit is configured to provide a voltage for the gate of the third normally-off transistor when the bidirectional switch is in the off-state and the second input-output terminal is at a higher potential than the first input-output terminal, and comprises a second step-down circuit configured to reduce the voltage applied to the gate of the third normally-off transistor.
7. The semiconductor device of claim 6 , wherein:
the first step-down circuit comprises a first ESD (electrostatic discharge) diode having an anode electrically connected to the source of the first normally-on transistor and a cathode electrically connected to the gate of the fourth normally-off transistor; and
the second step-down circuit comprises a second ESD diode having an anode electrically connected to the source of the second normally-on transistor and a cathode electrically connected to the gate of the third normally-off transistor.
8. The semiconductor device of claim 7 , wherein:
the first step-down circuit comprises a first gated diode device coupled antiparallel with the first ESD diode; and
the second step-down circuit comprises a second gated diode device coupled antiparallel with the second ESD diode.
9. The semiconductor device of claim 5 , wherein:
the third normally-off transistor is at least 10 times larger than the first normally-on transistor; and
the fourth normally-off transistor is at least 10 times larger than the second normally-on transistor.
10. The semiconductor device of claim 5 , wherein:
the gate of the first normally-off transistor is electrically connected to a cathode of a second ESD diode; and
the gate of the second normally-off transistor is electrically connected to a cathode of a first ESD diode.
11. The semiconductor device of claim 4 , wherein:
the gate of the first normally-off transistor is electrically connected to the substrate region; and
the gate of the second normally-off transistor is electrically connected to the substrate region.
12. The semiconductor device of claim 4 , wherein:
the first normally-on transistor and the first normally-off transistor of the first passive cascode circuit form the discharge path between the substrate region and the first input-output terminal; and
the second normally-on transistor and the second normally-off transistor of the second passive cascode circuit form the discharge path between the substrate region and the second input-output terminal.
13. The semiconductor device of claim 12 , wherein:
the first step-down circuit comprises a first ESD (electrostatic discharge) diode having an anode electrically connected to the source of the first normally-on transistor and a cathode electrically connected to the gate of the second normally-off transistor; and
the second step-down circuit comprises a second ESD diode having an anode electrically connected to the source of the second normally-on transistor and a cathode electrically connected to the gate of the first normally-off transistor.
14. The semiconductor device of claim 13 , wherein:
the first step-down circuit comprises a first gated diode device coupled antiparallel with the first ESD diode; and
the second step-down circuit comprises a second gated diode device coupled antiparallel with the second ESD diode.
15. The semiconductor device of claim 1 , wherein during ZVS (zero-voltage switching) of the bidirectional switch:
a potential difference between the second input-output terminal and the substrate region remains at or near zero volt during turn on of the bidirectional switch following an off-state of the bidirectional switch in which the first input-output terminal is at a higher potential than the second input-output terminal; and
a potential difference between the first input-output terminal and the substrate region remains at or near zero volt during turn on of the bidirectional switch following an off-state of the bidirectional switch in which the second input-output terminal is at a higher potential than the first input-output terminal.
16. The semiconductor device of claim 1 , wherein:
the first gate structure of the bidirectional switch is a normally-on gate structure; and
the second gate structure of the bidirectional switch is a normally-on gate structure.
17. The semiconductor device of claim 1 , wherein:
the first gate structure of the bidirectional switch is a normally-off gate structure; and
the second gate structure of the bidirectional switch is a normally-off gate structure.
18. The semiconductor device of claim 1 , wherein:
one of the first gate structure and the second gate structure of the bidirectional switch is a normally-on gate structure; and
the other one of the first gate structure and the second gate structure of the bidirectional switch is a normally-off gate structure.
19. A semiconductor device, comprising:
a semiconductor body comprising an active region and a substrate region beneath the active region;
a bidirectional switch comprising first and second gate structures configured to control a conductive state of a channel in the active region, and first and second input-output terminals electrically connected to the channel; and
a passive discharge circuit in parallel with the bidirectional switch and configured to utilize a fraction of a voltage across the first and second input-output terminals to switch on a transistor device that electrically connects the substrate region to the input-output terminal at the lower potential during an off-state of the bidirectional switch and during ZVS (zero-voltage switching) transition periods.