Semiconductor device and manufacturing method thereof
In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
1 . A method of manufacturing a negative capacitance fin field effect transistor (NC-FinFET), the method comprising:
forming a dummy gate structure over a fin structure;
forming a source/drain structure over the fin structure on opposing sides of the dummy gate structure;
forming an interlayer dielectric layer over the source/drain structure;
removing the dummy gate structure, thereby exposing a channel region of the fin structure;
forming an interfacial layer over the exposed fin structure;
forming a bottom crystal structure control layer;
forming a dielectric layer over the bottom crystal structure control layer;
after the dielectric layer is formed, converting the dielectric layer to a ferroelectric dielectric layer by performing an annealing operation followed by a cooling operation; and
forming a gate electrode including one or more metallic layers, wherein:
the ferroelectric dielectric layer comprises a (111) oriented orthorhombic crystal.
2 . The method of claim 1 , wherein the dielectric layer includes HfO 2 doped with one or more selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr.
3 . The method of claim 1 , wherein the ferroelectric dielectric layer includes Zr doped HfO 2 .
4 . The method of claim 1 , wherein the bottom crystal structure control layer includes ZrO 2 .
5 . The method of claim 4 , wherein the bottom crystal structure control layer is formed by atomic layer deposition.
6 . The method of claim 1 , wherein the annealing operation is performed at a temperature in a range from 700° C. to 1000° C. in an inert gas ambient.
7 . The method of claim 1 , wherein a thickness of the bottom crystal structure control layer is in a range from 0.5 nm to 1.0 nm.
8 . A method of manufacturing a negative capacitance fin field effect transistor (NC-FinFET), the method comprising:
forming a dummy gate structure over a fin structure;
forming a source/drain structure over the fin structure on opposing sides of the dummy gate structure;
forming an interlayer dielectric layer over the source/drain structure;
removing the dummy gate structure, thereby exposing a channel region of the fin structure;
forming an interfacial layer over the exposed fin structure;
forming a dielectric layer over the interfacial layer;
forming an upper crystal structure control layer over the dielectric layer;
after the dielectric layer is formed, converting the dielectric layer to a ferroelectric dielectric layer by performing an annealing operation followed by a cooling operation; and
forming a gate electrode including one or more metallic layers, wherein:
the ferroelectric dielectric layer comprises a (111) oriented orthorhombic crystal.
9 . The method of claim 8 , wherein the upper crystal structure control layer includes Si-doped TiN.
10 . The method of claim 9 , wherein the upper crystal structure control layer is formed by atomic layer deposition at a temperature in a range from 350° C. 450° C. using TiCl 4 and SiH 4 as precursors.
11 . The method of claim 10 , wherein the doped TiN is (111) oriented.
12 . The method of claim 8 , wherein the upper crystal structure control layer includes (111) oriented TaN or W.
13 . The method of claim 8 , wherein the dielectric layer includes HfO 2 doped with one or more selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr.
14 . The method of claim 8 , wherein the ferroelectric dielectric layer includes Zr doped HfO 2 .
15 . The method of claim 8 , wherein the annealing operation is performed at a temperature in a range from 700° C. to 1000° C. in an inert gas ambient for 10 sec to 1 min.
16 . A method of manufacturing a negative capacitance fin field effect transistor (NC-FinFET), the method comprising:
forming a dummy gate structure over a semiconductor layer;
forming a source/drain structure on opposing sides of the dummy gate structure;
forming an interlayer dielectric layer over the source/drain structure;
removing the dummy gate structure, thereby exposing a channel region of the semiconductor layer;
forming a bottom crystal structure control layer over the exposed semiconductor layer;
forming a stacked structure of first dielectric layers and second dielectric layers alternately stacked over the bottom crystal structure control layer;
forming an upper crystal structure control layer over the stacked structure;
after the upper crystal structure control layer is formed, converting the stacked structure to a single-layer ferroelectric dielectric layer by performing an annealing operation followed by a cooling operation; and
forming a gate electrode including one or more metallic layers, wherein:
the single-layer ferroelectric dielectric layer comprises a (111) oriented orthorhombic crystal.
17 . The method of claim 16 , wherein the first dielectric layers are made of HfO 2 and the second dielectric layers are made of ZrO 2 .
18 . The method of claim 17 , wherein the bottom crystal structure control layer includes ZrO 2 .
19 . The method of claim 18 , wherein a part of the bottom crystal structure control layer is converted to the single-layer ferroelectric dielectric layer.
20 . The method of claim 16 , wherein the annealing operation is performed at a temperature in a range from 700° C. to 1000° C. in an inert gas ambient for 10 sec to 1 min.