Semiconductor memory device
A semiconductor memory device includes a semiconductor substrate, a peripheral circuit structure disposed on the semiconductor substrate, and a cell array structure located on the peripheral circuit structure and including a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells of the cell array structure includes a bit line extending in a first horizontal direction, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a first word line extending in a second horizontal direction crossing the first horizontal direction on the channel pattern, a first gate insulating pattern located between the channel pattern and the first word line, a landing pad connected to the vertical channel portion of the channel pattern, and a data storage pattern disposed on the landing pad.
1 . A semiconductor memory device comprising:
a semiconductor substrate;
a peripheral circuit structure disposed on the semiconductor substrate; and
a cell array structure located on the peripheral circuit structure and including a memory cell array including a plurality of memory cells,
wherein the peripheral circuit structure includes:
a first transistor integrated on an upper surface of the semiconductor substrate, and
a connection wiring structure located on the first transistor and including a first connection wiring and a first connection contact plug electrically connecting the first connection wiring to the first transistor,
wherein each of the plurality of memory cells of the cell array structure includes:
a bit line extending in a first horizontal direction and electrically connected to the first connection wiring;
a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion;
a first word line extending in a second horizontal direction crossing the first horizontal direction on the channel pattern;
a first gate insulating pattern located between the channel pattern and the first word line;
a landing pad connected to the vertical channel portion of the channel pattern; and
a data storage pattern disposed on the landing pad,
wherein the first connection wiring and the first connection contact plug electrically connecting the bit line to the first transistor overlap the plurality of memory cells in a vertical direction, and
wherein the peripheral circuit structure includes a sense amplifier region, a sub-word line driver region, and a coupling region, and
wherein a portion of at least one of the sense amplifier region, the sub-word line driver region, and the coupling region overlaps the plurality of memory cells in the vertical direction.
2 . The semiconductor memory device of claim 1 , wherein the first transistor constitutes a sense amplifier located in the sense amplifier region.
3 . The semiconductor memory device of claim 1 , wherein
the connection wiring structure further includes:
a second connection wiring including a connection pad on the first connection wiring and a connection wiring line extending in the first horizontal direction; and
a second connection contact plug connecting the second connection wiring to the first connection wiring,
wherein the bit line is electrically connected to the first transistor through the connection pad and the second connection contact plug.
4 . The semiconductor memory device of claim 3 , further comprising:
a second transistor integrated on the upper surface of the semiconductor substrate and configuring a sub-word line driver located in the sub-word line driver region,
wherein the connection wiring line is electrically connected to the second transistor through the second connection contact plug, the first connection wiring, and the first connection contact plug, and
wherein the second connection contact plug overlaps the plurality of memory cells in the vertical direction.
5 . The semiconductor memory device of claim 1 , wherein the first word line includes a horizontal portion on the horizontal channel portion of the channel pattern and a vertical portion, on the vertical channel portion, protruding from the horizontal portion in the vertical direction.
6 . The semiconductor memory device of claim 5 , wherein
the horizontal portion of the first word line has a first thickness on an upper surface of the horizontal channel portion, and
the vertical portion of the first word line has a second thickness on a sidewall of the vertical channel portion, wherein the second thickness is substantially equal to the first thickness.
7 . The semiconductor memory device of claim 5 , wherein at least a portion of the horizontal portion of the first word line is buried in an upper portion of the bit line.
8 . The semiconductor memory device of claim 1 , further comprising:
a second word line,
wherein the first word line and the second word line are symmetrically disposed on the horizontal channel portion,
wherein each of the first word line and the second word line includes a horizontal portion on the horizontal channel portion and a vertical portion, on the vertical channel portion, protruding from the horizontal portion in the vertical direction.
9 . The semiconductor memory device of claim 8 , further comprising:
a second gate insulating pattern apart from the first gate insulating pattern and between the second word line and the channel pattern.
10 . A semiconductor memory device comprising:
a semiconductor substrate;
a peripheral circuit structure including a sense amplifier region disposed on the semiconductor substrate, in which a sense amplifier is located, a sub-word line driver region in which a sub-word line driver is located, and a coupling region in which a driving circuit driver and a switch for driving the sub-word line driver or the sense amplifier are located; and
a cell array structure located on the peripheral circuit structure and including a memory cell array including a plurality of memory cells each including a selection device and a data storage device,
wherein the selection device is a vertical channel transistor,
wherein at least a portion of at least one of the sense amplifier region, the sub-word line driver region, and the coupling region overlaps the plurality of memory cells in a vertical direction, and
wherein an electrical path of the plurality of memory cells and the sense amplifier overlaps the plurality of memory cells in the vertical direction.
11 . The semiconductor memory device of claim 10 , wherein at least a portion of the sense amplifier region overlaps the plurality of memory cells in the vertical direction.
12 . The semiconductor memory device of claim 11 , wherein
the peripheral circuit structure includes:
a first transistor integrated on an upper surface of the semiconductor substrate and constituting the sense amplifier; and
a connection wiring structure located on the first transistor and including a first connection wiring and a first connection contact plug electrically connecting the first connection wiring to the first transistor,
wherein each of the plurality of memory cells includes:
a bit line extending in a first horizontal direction and electrically connected to the first connection wiring;
a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion;
a word line extending in a second horizontal direction intersecting with the first horizontal direction on the channel pattern;
a gate insulating pattern located between the channel pattern and the word line;
a landing pad electrically connected to the vertical channel portion of the channel pattern; and
a data storage pattern disposed on the landing pad,
wherein the first connection wiring and the first connection contact plug electrically connecting the bit line to the first transistor vertically overlap the plurality of memory cells.
13 . The semiconductor memory device of claim 12 , wherein
the peripheral circuit structure further includes a second transistor integrated on the upper surface of the semiconductor substrate and constituting the sub-word line driver,
wherein the connection wiring structure further includes:
a second connection wiring including a connection pad on the first connection wiring and a connection wiring line extending in the first horizontal direction; and
a second connection contact plug electrically connecting the second connection wiring to the first connection wiring,
wherein the bit line is electrically connected to the first transistor through the connection pad and the second connection contact plug, and
wherein the connection wiring line is electrically connected to the second transistor through the second connection contact plug, the first connection wiring, and the first connection contact plug overlapping the plurality of memory cells in the vertical direction.
14 . The semiconductor memory device of claim 12 , wherein
the peripheral circuit structure further includes:
a peripheral contact plug electrically connected to the first transistor; and
a peripheral circuit wiring located between the peripheral contact plug and the first connection wiring.
15 . The semiconductor memory device of claim 11 , wherein
the sense amplifier region is positioned on a first horizontal direction side of the memory cell array, and the sub-word line driver region is positioned on a second horizontal direction side of the memory cell array, in a plan view.
16 . The semiconductor memory device of claim 11 , wherein the sense amplifier region is positioned on a second horizontal direction side of the memory cell array, and the sub-word line driver region is positioned on a first horizontal direction side of the memory cell array, in a plan view.
17 . A semiconductor memory device comprising:
a semiconductor substrate;
a peripheral circuit structure including a sense amplifier region disposed on the semiconductor substrate, in which a sense amplifier is located, a sub-word line driver region in which a sub-word line driver is located, and a coupling region in which a driving circuit driver and a switch for driving the sub-word line driver or the sense amplifier are located; and
a cell array structure disposed on the peripheral circuit structure and including a memory cell array constituted by a plurality of memory cells,
wherein the peripheral circuit structure includes:
a first transistor integrated on an upper surface of the semiconductor substrate and constituting the sense amplifier and a second transistor constituting the sub-word line driver;
a peripheral contact plug electrically connected to each of the first transistor and the second transistor;
a peripheral circuit wiring electrically connected to the peripheral contact plug; and
a connection wiring structure disposed on the peripheral circuit wiring and including a first connection wiring and a first connection contact plug electrically connecting the first connection wiring to the peripheral circuit wiring,
wherein each of the plurality of memory cells of the cell array structure includes:
a bit line extending in a first horizontal direction and electrically connected to the firs connection wiring;
a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion;
a first word line extending in a second horizontal direction intersecting with the first horizontal direction on the channel pattern;
a first gate insulating pattern located between the channel pattern and the first word line;
a landing pad electrically connected to the vertical channel portion of the channel pattern; and
a data storage pattern disposed on the landing pad,
wherein:
at least a portion of the sense amplifier region overlaps the plurality of memory cells in a vertical direction, and
the first connection wiring, the first connection contact plug, the peripheral circuit wiring, and the peripheral contact plug electrically connecting the bit line to the first transistor vertically overlap the plurality of memory cells.
18 . The semiconductor memory device of claim 17 , wherein
the connection wiring structure further includes:
a second connection wiring including a connection pad on the first connection wiring and a connection wiring line extending in the first horizontal direction; and
a second connection contact plug electrically connecting the second connection wiring to the first connection wiring,
wherein:
the bit line is electrically connected to the first transistor through the connection pad and the second connection contact plug,
at least a portion of the sub-word line driver region overlaps the plurality of memory cells in the vertical direction, and
the connection wiring line is electrically connected to the second transistor through the second connection contact plug, the first connection wiring, the first connection contact plug, the peripheral circuit wiring, and the peripheral contact plug overlapping the plurality of memory cells in the vertical direction.
19 . The semiconductor memory device of claim 17 , further comprising:
a second word line, and
a second gate insulating pattern located apart from the first gate insulating pattern and between the second word line and the channel pattern,
wherein the first and second word lines are symmetrically disposed on the horizontal channel portion, and
wherein each of the first word line and the second word line includes a horizontal portion on the horizontal channel portion and a vertical portion, on the vertical channel portion, protruding from the horizontal portion in the vertical direction.