Semiconductor device and method for fabricating the same
A semiconductor device includes: a bit line; an oxide semiconductor pillar extending vertically from the bit line; a capacitor over the oxide semiconductor pillar; and a word line disposed over a sidewall of the oxide semiconductor pillar, wherein the oxide semiconductor pillar includes: a lower oxide semiconductor interface layer coupled to the bit line; an upper oxide semiconductor interface layer coupled to the capacitor; and an oxide semiconductor channel layer between the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer.
1 . A semiconductor device, comprising:
a bit line over a substrate;
an oxide semiconductor pillar extending vertically from and over a top surface of the bit line;
a first contact plug disposed over the oxide semiconductor pillar;
a second contact plug disposed over the first contact plug, the first contact plug having a top surface that is at least partially in contact with a bottom surface of the second contact plug;
a capacitor disposed over the second contact plug; and
a word line comprising two separate word line structures having shapes that are symmetrical to each other, each word line structure being disposed over at least some sidewalls of the oxide semiconductor pillar and the first contact plug and under the second contact plug,
wherein the oxide semiconductor pillar comprises:
a lower oxide semiconductor interface layer coupled to the bit line;
an upper oxide semiconductor interface layer coupled to the capacitor; and
an oxide semiconductor channel layer disposed between the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer.
2 . The semiconductor device of claim 1 , wherein the word line structure has a tapered shape.
3 . The semiconductor device of claim 1 , wherein the word line structure includes
an upper level portion disposed adjacent to the capacitor, and
a lower level portion disposed adjacent to the bit line, and wherein the lower level portion is thinner than the upper level portion.
4 . The semiconductor device of claim 1 , wherein the bit line includes a metal material.
5 . The semiconductor device of claim 1 , further comprising:
a barrier layer disposed between the bit line and the lower oxide semiconductor interface layer.
6 . The semiconductor device of claim 1 , further comprising:
a buffer layer disposed between the bit line and the substrate.
7 . The semiconductor device of claim 1 , wherein each of the oxide semiconductor channel layer, the lower oxide semiconductor interface layer, and the upper oxide semiconductor interface layer includes an oxide semiconductor material, and
wherein the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer include an oxide semiconductor material having a lower resistance than the oxide semiconductor channel layer.
8 . The semiconductor device of claim 1 , wherein the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer include a metallic-rich oxide semiconductor material having a greater metallic component than the oxide semiconductor channel layer.
9 . The semiconductor device of claim 1 , wherein the oxide semiconductor channel layer includes IGZO, ITZO or ZTO, and
the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer include indium-rich IGZO, and
the indium-rich IGZO includes IGZO with a greater content of indium than gallium and zinc.
10 . The semiconductor device of claim 1 , further comprising:
a dummy plate which is disposed at a lower level than the bit line, and
wherein the dummy plate and the bit line are coupled to each other.
11 . The semiconductor device of claim 1 , wherein a height of the oxide semiconductor channel layer is greater than a height of the lower oxide semiconductor interface layer and a height of the upper oxide semiconductor interface layer.
12 . The semiconductor device of claim 1 , further comprising:
a gate dielectric layer disposed between the oxide semiconductor channel layer and each of the two separate word line structures,
wherein the gate dielectric layer includes:
a vertical portion which is disposed between the oxide semiconductor channel layer and each of the two separate word line structures; and
a horizontal portion which extends from the vertical portion and is disposed between the bit line and each of the two separate word line structures.
13 . The semiconductor device of claim 1 , further comprising:
a gate dielectric layer between the oxide semiconductor channel layer and each of the two separate word line structures; and
an isolating dielectric layer between each of the two separate word line structures and the bit line,
wherein the gate dielectric layer includes a horizontal portion extending to be disposed between each of the two separate word line structures and the bit line.
14 . The semiconductor device of claim 13 , wherein the isolating dielectric layer is disposed over or under the gate dielectric layer.
15 . The semiconductor device of claim 13 , wherein a height of the lower oxide semiconductor interface layer and a height of a horizontal portion of the isolating dielectric layer are greater than a height of the upper oxide semiconductor interface layer.
16 . A semiconductor device, comprising:
a substrate;
a peripheral circuit portion disposed over the substrate; and
a memory cell array including a bit line over the substrate, a transistor over the bit line, a second contact plug over the transistor, and a memory element that is vertically stacked over the peripheral circuit portion and the second contact plug,
wherein the transistor comprises:
an oxide semiconductor channel layer disposed between the bit line and the memory element;
a first contact plug disposed over an upper oxide semiconductor interface layer, the first contact plug having a top surface that is at least partially in contact with a bottom surface of the second contact plug;
two separate tapered vertical word line structures having shapes that are symmetrical to each other, each tapered word line structure being disposed over at least some sidewalls of the oxide semiconductor channel layer and the first contact plug and under the second contact plug;
a lower oxide semiconductor interface layer disposed between the bit line and the oxide semiconductor channel layer; and
the upper oxide semiconductor interface layer disposed between the memory element and the oxide semiconductor channel layer.
17 . The semiconductor device of claim 16 , wherein the tapered vertical word line structure includes:
an upper level portion disposed adjacent to the memory element, and
a lower level portion disposed adjacent to the bit line and thinner than the upper level portion.
18 . The semiconductor device of claim 16 , wherein the bit line includes a metal material.
19 . The semiconductor device of claim 16 , wherein the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer include an oxide semiconductor material which has a lower resistance than the oxide semiconductor channel layer.
20 . The semiconductor device of claim 16 , wherein the oxide semiconductor channel layer includes IGZO, ITZO or ZTO, and
the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer include indium-rich IGZO, and
the indium-rich IGZO includes IGZO with a greater content of indium than gallium and zinc.
21 . A semiconductor device, comprising:
a first conductive line over a substrate;
an oxide semiconductor pillar extending vertically from and over a top surface of the first conductive line;
a first contact plug disposed over the oxide semiconductor pillar;
a second contact plug disposed over the first contact plug, the first contact plug having a top surface that is at least partially in contact with a bottom surface of the second contact plug;
a capacitor disposed over the second contact plug; and
two separate second tapered conductive lines having shapes that are symmetrical to each other, each second tapered conductive line being disposed over at least some sidewalls of the oxide semiconductor pillar and the first contact plug and under the second contact plug,
wherein the oxide semiconductor pillar comprises:
a lower oxide semiconductor interface layer coupled to the first conductive line;
an upper oxide semiconductor interface layer coupled to the capacitor; and
an oxide semiconductor channel layer disposed between the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer.