Granted Patent B2

US 11,720,736 · App. 18/111,567 · Granted Aug 8, 2023

Inventors: Zvi Or-Bach (Haifa, IL); Zeev Wurman (Palo Alto, CA)

G06F30/392G06F30/394

Abstract

Claims (79)

1. A method of designing a 3D Integrated Circuit, the method comprising:

partitioning at least one design into at least two levels, a first level and a second level,

wherein said first level comprises a plurality of first transistors,

wherein said second level comprises a plurality of second transistors, and

wherein said second level is on top of said first level;

providing placement data of said second level;

performing a placement of said first level using a placer program executed by a computer,

wherein said placement of said first level is based on said placement data,

wherein said placer is part of a Computer Aided Design (CAD) tool, and

wherein said first level comprises first routing layers; and

performing a routing of said first level by routing layers using a router executed by a computer,

wherein said router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool, and

wherein at least one metal routing layer is disposed in-between said plurality of first transistors and said plurality of second transistors.

2. The method according to claim 1 ,

wherein a majority area of said second level comprises memory.

3. The method according to claim 1 ,

wherein results of said second level is a generic structure.

4. The method according to claim 1 ,

wherein said first level is designed to be processed with a different process node than a process node used for said second level.

5. The method according to claim 1 , further comprising:

providing connections placement data of said second level,

wherein said connections comprise planned connections between said first level and said second level.

6. The method according to claim 1 ,

wherein said first level comprises Input and Output cells (“IO”).

7. The method according to claim 1 ,

wherein said second level comprises one or more RF (Radio Frequency) circuits.

8. A method of designing a 3D Integrated Circuit, the method comprising:

partitioning at least one design into at least two levels, a first level and a second level,

wherein said first level comprises a plurality of first transistors,

wherein said second level comprises a plurality of second transistors,

wherein said second level is on top of said first level,

wherein a majority area of said first level comprises logic circuits, and

wherein a substantial area of said second level comprises analog circuits;

providing connections placement data of said second level,

wherein said connections comprise planned connections between said first level and said second level;

performing a placement of said first level using a placer program executed by a computer,

wherein said placer is part of a Computer Aided Design (CAD) tool, and

wherein said first level comprises first routing layers; and

performing a routing of said first level by routing layers using a router executed by a computer,

wherein said router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.

9. The method according to claim 8 ,

wherein said placement of said first level is based on said connections placement data.

10. The method according to claim 8 ,

wherein at least one metal routing layer is disposed in-between said plurality of first transistors and said plurality of second transistors.

11. The method according to claim 8 ,

wherein said first level is designed to be processed with a different process node than a process node used for said second level.

12. The method according to claim 8 ,

wherein said connections are located in a top layer of said second level, and

wherein said connections are available for connection to said first level.

13. The method according to claim 8 ,

wherein said first level comprises Input and Output cells (“IO”).

14. The method according to claim 8 ,

wherein said second level comprises one or more RF (Radio Frequency) circuits.

15. A method of designing a 3D Integrated Circuit, the method comprising:

partitioning at least one design into at least two levels, a first level and a second level,

wherein said first level comprises a plurality of first transistors,

wherein said second level comprises a plurality of second transistors,

wherein said second level is on top of said first level;

providing connections placement data of said second level,

wherein said connections comprise planned connections between said first level and said second level;

performing a placement of said first level using a placer program executed by a computer,

wherein said placer is part of a Computer Aided Design (CAD) tool, and

wherein said first level comprises first routing layers; and

performing a routing of said first routing layers using a router executed by a computer,

wherein said router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool,

wherein said second level comprises circuits designed for non-advanced process nodes, and

wherein said first level comprises circuits designed for an advanced process node.

16. The method according to claim 15 ,

wherein a majority area of said first level comprises logic circuits.

17. The method according to claim 15 ,

wherein at least one metal routing layer is disposed in-between said plurality of first transistors and said plurality of second transistors.

18. The method according to claim 15 , further comprising:

providing placement data of said first level; and

performing a placement of said second level using a placer executed by a computer,

wherein said placement of said second level is based on said placement data.

19. The method according to claim 15 ,

wherein said placement of said first level is based on said connections placement data.

20. The method according to claim 15 ,

wherein said first level comprises Input and Output cells (“IO”).

Continuity (12)