Structure of package substrate
A structure of a package substrate includes: a first multi-layer substrate including a plurality of dielectric layers and a plurality of metal wiring layers and having a first surface and a second surface which are opposite to each other; and a supporting substrate having a first surface and a second surface which are opposite to each other, wherein the first surface of the supporting substrate is disposed on the second surface of the first multi-layer substrate and electrically connected to the first multi-layer substrate, there is no gap between the first surface of the supporting substrate and the second surface of the first multi-layer substrate, the supporting substrate includes a plurality of vertical vias, and the vertical vias are used for electrically connecting the first surface of the supporting substrate to the second surface of the supporting substrate.
1. A structure of a package substrate, comprising:
a first multi-layer substrate comprising a plurality of dielectric layers and a plurality of metal wiring layers and having a first surface and a second surface which are opposite to each other,
wherein the dielectric layers and the metal wiring layers are alternately stacked, the dielectric layers are adhered to each other,
the metal wiring layers are individually embedded in the corresponding dielectric layers, and
a dielectric layer of the plurality of dielectric layers located in the first surface of the multi-layer substrate is used as a solder mask layer which is embedded with at least one pad layer; and
a supporting substrate having a first surface and a second surface which are opposite to each other,
wherein the first surface of the supporting substrate is disposed on the second surface of the first multi-layer substrate and electrically connected to the first multi-layer substrate,
there is no gap between the first surface of the supporting substrate and the second surface of the first multi-layer substrate,
the supporting substrate comprises a plurality of vertical vias, the vertical vias are used for electrically connecting the first surface of the supporting substrate to the second surface of the supporting substrate, and
at least one electrical connection point is disposed on the second surface of the supporting substrate to electrically connect to a circuit board or an electronic component.
2. The structure of the package substrate according to claim 1 , further comprising a second multi-layer substrate, wherein at least one electrical connection point is disposed on the second surface of the supporting substrate to electrically connect to the second multi-layer substrate, and the second multi-layer substrate is used for electrically connecting to a circuit board or an electronic component.
3. The structure of the package substrate according to claim 1 , wherein the supporting substrate is a crystal-grown ceramic substrate, and a material of the crystal-grown ceramic substrate includes aluminum oxide crystals or aluminum nitride crystals.
4. The structure of the package substrate according to claim 1 , wherein at least one electrical connection point of a bare die is electrically and correspondingly connected to the at least one pad layer in the first surface of the first multi-layer substrate to complete an electrical connection.
5. The structure of the package substrate according to claim 2 , wherein there is no gap between the second surface of the second multi-layer substrate and the supporting substrate, and horizontal stress of the first multi-layer substrate against the supporting substrate and horizontal stress of the second multi-layer substrate against the supporting substrate are substantially the same.
6. The structure of the package substrate according to claim 2 , wherein at least one electrical connection point of a bare die is electrically and correspondingly connected to the at least one pad layer in the first surface of the first multi-layer substrate to complete an electrical connection.
7. The structure of the package substrate according to claim 1 , wherein the at least one pad layer is completely or partially embedded in the dielectric layer in the first surface of the first multi-layer substrate, and there is no height difference between an upper surface of the at least one pad layer and an upper surface of the dielectric layer in the first surface of the first multi-layer substrate.
8. The structure of the package substrate according to claim 1 , wherein a material of each of the dielectric layers of the first multi-layer substrate is polyimide.
9. The structure of the package substrate according to claim 1 , wherein the first multi-layer substrate further comprises a plurality of vias disposed in the dielectric layers and used for connecting the metal wiring layers.