Fabrication method for JFET with implant isolation

1. A method of manufacturing a vertical junction field effect transistor (JFET), the method comprising:

providing a semiconductor substrate of a first conductivity type and having a first surface and a second surface;

forming a plurality of fins coupled to the semiconductor substrate;

forming a gate layer of a second conductivity type opposite the first conductivity type surrounding the plurality of fins; and

concurrently:

forming an isolation region surrounding the plurality of fins; and

forming a body diode region surrounding the isolation region.

2. The method of claim 1 wherein forming the plurality of fins comprises:

forming a first epitaxial semiconductor layer of the first conductivity type on the first surface of the semiconductor substrate;

forming a second epitaxial semiconductor layer of the first conductivity type on the first epitaxial semiconductor layer;

forming a first patterned hard mask layer on the second epitaxial semiconductor layer;

etching a portion of the second epitaxial semiconductor layer using the first patterned hard mask layer as a mask to form the plurality of fins on the first epitaxial semiconductor layer and a recess region surrounding the plurality of fins; and

filling the recess region with the gate layer.

3. The method of claim 2 further comprising:

removing the first patterned hard mask layer;

forming a second patterned hard mask layer covering the plurality of fins while exposing a surface portion of the gate layer; and

etching the exposed surface portion of the gate layer using the second patterned hard mask layer as a mask to form a second trench configured to be the isolation region.

4. The method of claim 2 further comprising:

removing the first patterned hard mask layer; and

forming a second patterned hard mask layer covering the plurality of fins while exposing a surface portion of the gate layer;

wherein forming the isolation region comprises implanting an n-type impurity into the exposed surface portion of the gate layer using an ion implantation process.

5. The method of claim 4 wherein implanting the n-type impurity forms an n-type doped region.

6. The method of claim 2 further comprising:

forming a metal layer on an upper portion of the plurality of fins, on an upper portion of the gate layer, and on an upper portion of the body diode region;

forming an interlayer dielectric layer on the metal layer, the gate layer, and the isolation region;

forming a third patterned hard mask layer on the interlayer dielectric layer on the metal layer;

etching the interlayer dielectric layer using the third patterned hard mask layer as a mask to forming a plurality of through-holes exposing a surface portion of the metal layer on the upper portion of the plurality of fins and on the upper portion of the body diode region; and

filling the through-holes with a conductive material to form a plurality of vias.

7. The method of claim 6 further comprising:

forming a source metal layer coupled to the plurality of vias; and

forming a drain metal layer on the second surface of the semiconductor substrate.

8. The method of claim 2 wherein forming the gate layer comprises epitaxially growing a third epitaxial semiconductor layer of the second conductivity type on the second epitaxial semiconductor layer having a first portion surrounding the plurality of fins and a second portion on an opposite side of the isolation region.

9. The method of claim 8 wherein the second portion of the second epitaxial semiconductor layer forms a portion of the body diode region.

10. The method of claim 9 wherein:

the second portion of the third epitaxial semiconductor layer forms an anode of a p-n junction diode;

the second portion of the second epitaxial semiconductor layer forms a cathode of a Schottky barrier diode;

a second portion of the first epitaxial semiconductor layer forms a cathode of a p-n junction diode; and

the second portion of the first epitaxial semiconductor layer is further coupled to the second epitaxial semiconductor layer to comprise a portion of the cathode of a Schottky barrier diode.

11. The method of claim 10 wherein:

an anode metal layer is formed in the body diode region;

the anode metal layer forms an ohmic contact to the second portion of the third epitaxial semiconductor layer; and

the anode metal layer forms a Schottky barrier diode anode to the second portion of the second epitaxial semiconductor layer.

12. The method of claim 11 further comprising:

forming a source metal contact layer on each of the plurality of fins fabricated in the first portion of the second epitaxial semiconductor layer;

forming a gate metal contact layer on the first portion of the third epitaxial semiconductor layer;

forming a dielectric layer on the source metal contact layer, the gate layer, the gate metal contact layer, the isolation region, the anode metal layer, and the body diode region;

forming a photomask on the dielectric layer to define through-hole locations;

etching the dielectric layer to form through-holes terminating on the source metal contact layer, the gate metal contact layer, and the anode metal layer;

removing the photomask;

filling the through-holes with a conductive metal layer;

forming a source metal layer; and

forming a drain layer.

13. The method of claim 12 wherein the source contact metal layer is electrically coupled to the anode metal layer.

14. The method of claim 8 wherein the second portion of the third epitaxial semiconductor layer forms an anode of a body diode, and a portion of the first epitaxial semiconductor layer below the second portion of the third epitaxial semiconductor layer forms a cathode of the body diode.

15. The method of claim 14 further comprising:

forming a source metal layer; and

forming a drain metal layer on the second surface of the semiconductor substrate.

16. The method of claim 15 wherein:

the anode of the body diode is coupled to the source metal layer; and

the cathode of the body diode is coupled to the drain metal layer.

17. The method of claim 1 further comprising an edge termination region surrounding the body diode region.

18. The method of claim 1 wherein the isolation region comprises a trap-rich implanted region.

19. The method of claim 1 wherein the plurality of fins further includes a contact region coupled to each of the plurality of fins.

20. The method of claim 19 wherein the contact region is electrically connected to an anode of a body diode in the body diode region.