Profile control of epitaxial structures in semiconductor devices
View Patent ↗A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a first FET, and a second FET. The first FET includes first and second fin structures disposed on first and second fin bases, respectively, a first S/D region disposed on the first and second fin bases and in contact with side surfaces of the first and second fin structures, and a first pair of spacers disposed on opposite sidewalls of the first S/D region. The second FET includes third and fourth fin structures disposed on third and fourth fin bases, respectively, a second S/D region disposed on the third and fourth fin structures, and a second pair of spacers disposed on opposite sidewalls of the second S/D region. A height of the first pair of spacers is greater than a height of the second pair of spacers.
1 . A semiconductor device, comprising:
a substrate comprising first and second substrate regions;
a first field effect transistor (FET), comprising:
first and second fin bases disposed on the first substrate region,
first and second fin structures disposed on the first and second fin bases, respectively,
a first source/drain (S/D) region in contact with top surfaces of the first and second fin bases and in contact with side surfaces of the first and second fin structures, and
a first pair of spacers disposed on opposite sidewalls of the first S/D region; and
a second FET, comprising:
third and fourth fin bases disposed on the second substrate region;
third and fourth fin structures disposed on the third and fourth fin bases, respectively;
a second S/D region in contact with top surfaces of the third and fourth fin structures; and
a second pair of spacers disposed on opposite sidewalls of the second S/D region,
wherein a height of the first pair of spacers is greater than a height of the second pair of spacers.
2 . The semiconductor device of claim 1 , wherein a distance between the first and second fin structures is less than a distance between the third and fourth fin structures.
3 . The semiconductor device of claim 1 , wherein widths of the first and second fin structures are greater than widths of the third and fourth fin structures.
4 . The semiconductor device of claim 1 , wherein a first merged region of the first S/D region extends above the first pair of spacers and a second merged region of the second S/D region extends above the second pair of spacers, and
wherein a thickness of the second merged region is greater than a thickness of the first merged region.
5 . The semiconductor device of claim 4 , wherein a ratio of a width of the second merged region to a width of the first merged region is about 1.1 to about 2.
6 . The semiconductor device of claim 1 , wherein a distance between top ends of the first and second fin structures is greater than a distance between bottom ends of the first and second fin structures; and
wherein a distance between top ends of the third and fourth fin structures is less than a distance between bottom ends of the third and fourth fin structures.
7 . The semiconductor device of claim 1 , wherein the second pair of spacers is disposed on opposite sidewalls of the third fin structure.
8 . The semiconductor device of claim 1 , wherein a difference between the height of the first pair of spacers and the height of the second pair of spacers is about 5 nm to about 10 nm.
9 . The semiconductor device of claim 1 , wherein the first S/D region has p-type dopants and the second S/D region has n-type dopants.
10 . The semiconductor device of claim 1 , wherein the third and fourth fin structures comprise undoped semiconductor materials.
11 . A semiconductor device, comprising:
a substrate comprising first and second substrate regions;
a first field effect transistor (FET), comprising:
a first fin base disposed on the first substrate region,
a first fin structures disposed on the first fin base,
a first source/drain (S/D) region disposed on the first fin base, and
a first pair of spacers disposed on opposite sidewalls of the first S/D region; and
a second FET, comprising:
a second fin base disposed on the second substrate region;
a second fin structure disposed on the second fin base, wherein the second fin structure comprises an undoped semiconductor material;
a second S/D region disposed on the second fin structure; and
a second pair of spacers disposed on opposite sidewalls of the second S/D region,
wherein a height of the first pair of spacers is greater than a height of the second pair of spacers.
12 . The semiconductor device of claim 11 , wherein the first S/D region comprises a diamond-shaped region above the first pair of spacers; and
wherein the second S/D region comprises an oval-shaped region above the second pair of spacers.
13 . The semiconductor device of claim 12 , wherein a width of the diamond-shaped region is greater than a width of the oval-shaped region.
14 . The semiconductor device of claim 11 , wherein a width of the first fin structure is greater than a width of the second fin structure.
15 . The semiconductor device of claim 11 , wherein a difference between the height of the first pair of spacers and the height of the second pair of spacers is about 5 nm to about 10 nm.
16 . The semiconductor device of claim 11 , wherein the first S/D region has p-type dopants and the second S/D region has n-type dopants.
17 . A method, comprising:
forming first and second fin structures on first and second fin bases, respectively, on a substrate;
forming third and fourth fin structures on third and fourth fin bases, respectively, on the substrate;
depositing a dielectric layer on the first, second, third, and fourth fin structures;
forming first source/drain (S/D) openings on the first and second fin bases and adjacent to the first and second fin structures, wherein forming the first S/D openings comprises:
etching portions of the first and second fin structures, and
etching portions of the first and second fin bases under the portions of the first and second fin structures;
etching a first portion of the dielectric layer to form first spacers on sidewalls of the first openings;
forming second S/D openings on the third and fourth fin structures;
etching a second portion of the dielectric layer to form second spacers on sidewalls of the second S/D openings;
forming a first merged S/D region in the first S/D openings; and
forming a second merged S/D region in the second S/D openings.
18 . The method of claim 17 , wherein the first spacers are formed with a first height and the second spacers are formed with a second height, and
wherein the first height is greater than the second height.
19 . The method of claim 17 , wherein forming the second S/D openings comprises etching portions of the third and fourth fin structures from a first height to a second height, wherein the second height is less than a height of the second spacers.
20 . The method of claim 17 , wherein forming first and second fin structures on first and second fin bases, respectively, comprises:
epitaxially growing a semiconductor layer on the substrate;
etching the semiconductor layer to form the first and second fin structures; and
etching portions of the substrate under the first and second fin structures to form the first and second fin bases.